1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SGI UV IRQ definitions 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _ASM_X86_UV_UV_IRQ_H 12*4882a593Smuzhiyun #define _ASM_X86_UV_UV_IRQ_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* If a generic version of this structure gets defined, eliminate this one. */ 15*4882a593Smuzhiyun struct uv_IO_APIC_route_entry { 16*4882a593Smuzhiyun __u64 vector : 8, 17*4882a593Smuzhiyun delivery_mode : 3, 18*4882a593Smuzhiyun dest_mode : 1, 19*4882a593Smuzhiyun delivery_status : 1, 20*4882a593Smuzhiyun polarity : 1, 21*4882a593Smuzhiyun __reserved_1 : 1, 22*4882a593Smuzhiyun trigger : 1, 23*4882a593Smuzhiyun mask : 1, 24*4882a593Smuzhiyun __reserved_2 : 15, 25*4882a593Smuzhiyun dest : 32; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun enum { 29*4882a593Smuzhiyun UV_AFFINITY_ALL, 30*4882a593Smuzhiyun UV_AFFINITY_NODE, 31*4882a593Smuzhiyun UV_AFFINITY_CPU 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun extern int uv_irq_2_mmr_info(int, unsigned long *, int *); 35*4882a593Smuzhiyun extern int uv_setup_irq(char *, int, int, unsigned long, int); 36*4882a593Smuzhiyun extern void uv_teardown_irq(unsigned int); 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #endif /* _ASM_X86_UV_UV_IRQ_H */ 39