1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _ASM_X86_PROCESSOR_FLAGS_H 3*4882a593Smuzhiyun #define _ASM_X86_PROCESSOR_FLAGS_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <uapi/asm/processor-flags.h> 6*4882a593Smuzhiyun #include <linux/mem_encrypt.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifdef CONFIG_VM86 9*4882a593Smuzhiyun #define X86_VM_MASK X86_EFLAGS_VM 10*4882a593Smuzhiyun #else 11*4882a593Smuzhiyun #define X86_VM_MASK 0 /* No VM86 support */ 12*4882a593Smuzhiyun #endif 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * CR3's layout varies depending on several things. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * If CR4.PCIDE is set (64-bit only), then CR3[11:0] is the address space ID. 18*4882a593Smuzhiyun * If PAE is enabled, then CR3[11:5] is part of the PDPT address 19*4882a593Smuzhiyun * (i.e. it's 32-byte aligned, not page-aligned) and CR3[4:0] is ignored. 20*4882a593Smuzhiyun * Otherwise (non-PAE, non-PCID), CR3[3] is PWT, CR3[4] is PCD, and 21*4882a593Smuzhiyun * CR3[2:0] and CR3[11:5] are ignored. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * In all cases, Linux puts zeros in the low ignored bits and in PWT and PCD. 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * CR3[63] is always read as zero. If CR4.PCIDE is set, then CR3[63] may be 26*4882a593Smuzhiyun * written as 1 to prevent the write to CR3 from flushing the TLB. 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * On systems with SME, one bit (in a variable position!) is stolen to indicate 29*4882a593Smuzhiyun * that the top-level paging structure is encrypted. 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * All of the remaining bits indicate the physical address of the top-level 32*4882a593Smuzhiyun * paging structure. 33*4882a593Smuzhiyun * 34*4882a593Smuzhiyun * CR3_ADDR_MASK is the mask used by read_cr3_pa(). 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #ifdef CONFIG_X86_64 37*4882a593Smuzhiyun /* Mask off the address space ID and SME encryption bits. */ 38*4882a593Smuzhiyun #define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull) 39*4882a593Smuzhiyun #define CR3_PCID_MASK 0xFFFull 40*4882a593Smuzhiyun #define CR3_NOFLUSH BIT_ULL(63) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #else 43*4882a593Smuzhiyun /* 44*4882a593Smuzhiyun * CR3_ADDR_MASK needs at least bits 31:5 set on PAE systems, and we save 45*4882a593Smuzhiyun * a tiny bit of code size by setting all the bits. 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun #define CR3_ADDR_MASK 0xFFFFFFFFull 48*4882a593Smuzhiyun #define CR3_PCID_MASK 0ull 49*4882a593Smuzhiyun #define CR3_NOFLUSH 0 50*4882a593Smuzhiyun #endif 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #ifdef CONFIG_PAGE_TABLE_ISOLATION 53*4882a593Smuzhiyun # define X86_CR3_PTI_PCID_USER_BIT 11 54*4882a593Smuzhiyun #endif 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif /* _ASM_X86_PROCESSOR_FLAGS_H */ 57