1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
4*4882a593Smuzhiyun * for more details.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Numascale NumaConnect-Specific Header file
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Copyright (C) 2011 Numascale AS. All rights reserved.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Send feedback to <support@numascale.com>
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #ifndef _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
15*4882a593Smuzhiyun #define _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/smp.h>
18*4882a593Smuzhiyun #include <linux/io.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define CSR_NODE_SHIFT 16
21*4882a593Smuzhiyun #define CSR_NODE_BITS(p) (((unsigned long)(p)) << CSR_NODE_SHIFT)
22*4882a593Smuzhiyun #define CSR_NODE_MASK 0x0fff /* 4K nodes */
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* 32K CSR space, b15 indicates geo/non-geo */
25*4882a593Smuzhiyun #define CSR_OFFSET_MASK 0x7fffUL
26*4882a593Smuzhiyun #define CSR_G0_NODE_IDS (0x008 + (0 << 12))
27*4882a593Smuzhiyun #define CSR_G3_EXT_IRQ_GEN (0x030 + (3 << 12))
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun * Local CSR space starts in global CSR space with "nodeid" = 0xfff0, however
31*4882a593Smuzhiyun * when using the direct mapping on x86_64, both start and size needs to be
32*4882a593Smuzhiyun * aligned with PMD_SIZE which is 2M
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun #define NUMACHIP_LCSR_BASE 0x3ffffe000000ULL
35*4882a593Smuzhiyun #define NUMACHIP_LCSR_LIM 0x3fffffffffffULL
36*4882a593Smuzhiyun #define NUMACHIP_LCSR_SIZE (NUMACHIP_LCSR_LIM - NUMACHIP_LCSR_BASE + 1)
37*4882a593Smuzhiyun #define NUMACHIP_LAPIC_BITS 8
38*4882a593Smuzhiyun
lcsr_address(unsigned long offset)39*4882a593Smuzhiyun static inline void *lcsr_address(unsigned long offset)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun return __va(NUMACHIP_LCSR_BASE | (1UL << 15) |
42*4882a593Smuzhiyun CSR_NODE_BITS(0xfff0) | (offset & CSR_OFFSET_MASK));
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
read_lcsr(unsigned long offset)45*4882a593Smuzhiyun static inline unsigned int read_lcsr(unsigned long offset)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun return swab32(readl(lcsr_address(offset)));
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
write_lcsr(unsigned long offset,unsigned int val)50*4882a593Smuzhiyun static inline void write_lcsr(unsigned long offset, unsigned int val)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun writel(swab32(val), lcsr_address(offset));
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * On NumaChip2, local CSR space is 16MB and starts at fixed offset below 4G
57*4882a593Smuzhiyun */
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #define NUMACHIP2_LCSR_BASE 0xf0000000UL
60*4882a593Smuzhiyun #define NUMACHIP2_LCSR_SIZE 0x1000000UL
61*4882a593Smuzhiyun #define NUMACHIP2_APIC_ICR 0x100000
62*4882a593Smuzhiyun #define NUMACHIP2_TIMER_DEADLINE 0x200000
63*4882a593Smuzhiyun #define NUMACHIP2_TIMER_INT 0x200008
64*4882a593Smuzhiyun #define NUMACHIP2_TIMER_NOW 0x200018
65*4882a593Smuzhiyun #define NUMACHIP2_TIMER_RESET 0x200020
66*4882a593Smuzhiyun
numachip2_lcsr_address(unsigned long offset)67*4882a593Smuzhiyun static inline void __iomem *numachip2_lcsr_address(unsigned long offset)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun return (void __iomem *)__va(NUMACHIP2_LCSR_BASE |
70*4882a593Smuzhiyun (offset & (NUMACHIP2_LCSR_SIZE - 1)));
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
numachip2_read32_lcsr(unsigned long offset)73*4882a593Smuzhiyun static inline u32 numachip2_read32_lcsr(unsigned long offset)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun return readl(numachip2_lcsr_address(offset));
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
numachip2_read64_lcsr(unsigned long offset)78*4882a593Smuzhiyun static inline u64 numachip2_read64_lcsr(unsigned long offset)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun return readq(numachip2_lcsr_address(offset));
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
numachip2_write32_lcsr(unsigned long offset,u32 val)83*4882a593Smuzhiyun static inline void numachip2_write32_lcsr(unsigned long offset, u32 val)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun writel(val, numachip2_lcsr_address(offset));
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
numachip2_write64_lcsr(unsigned long offset,u64 val)88*4882a593Smuzhiyun static inline void numachip2_write64_lcsr(unsigned long offset, u64 val)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun writeq(val, numachip2_lcsr_address(offset));
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
numachip2_timer(void)93*4882a593Smuzhiyun static inline unsigned int numachip2_timer(void)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun return (smp_processor_id() % 48) << 6;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun #endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */
99