1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef _ASM_X86_INTEL_PUNIT_IPC_H_
3*4882a593Smuzhiyun #define _ASM_X86_INTEL_PUNIT_IPC_H_
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun /*
6*4882a593Smuzhiyun * Three types of 8bit P-Unit IPC commands are supported,
7*4882a593Smuzhiyun * bit[7:6]: [00]: BIOS; [01]: GTD; [10]: ISPD.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun typedef enum {
10*4882a593Smuzhiyun BIOS_IPC = 0,
11*4882a593Smuzhiyun GTDRIVER_IPC,
12*4882a593Smuzhiyun ISPDRIVER_IPC,
13*4882a593Smuzhiyun RESERVED_IPC,
14*4882a593Smuzhiyun } IPC_TYPE;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define IPC_TYPE_OFFSET 6
17*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_CMD_BASE (BIOS_IPC << IPC_TYPE_OFFSET)
18*4882a593Smuzhiyun #define IPC_PUNIT_GTD_CMD_BASE (GTDDRIVER_IPC << IPC_TYPE_OFFSET)
19*4882a593Smuzhiyun #define IPC_PUNIT_ISPD_CMD_BASE (ISPDRIVER_IPC << IPC_TYPE_OFFSET)
20*4882a593Smuzhiyun #define IPC_PUNIT_CMD_TYPE_MASK (RESERVED_IPC << IPC_TYPE_OFFSET)
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* BIOS => Pcode commands */
23*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_ZERO (IPC_PUNIT_BIOS_CMD_BASE | 0x00)
24*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_VR_INTERFACE (IPC_PUNIT_BIOS_CMD_BASE | 0x01)
25*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_READ_PCS (IPC_PUNIT_BIOS_CMD_BASE | 0x02)
26*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_WRITE_PCS (IPC_PUNIT_BIOS_CMD_BASE | 0x03)
27*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_READ_PCU_CONFIG (IPC_PUNIT_BIOS_CMD_BASE | 0x04)
28*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_WRITE_PCU_CONFIG (IPC_PUNIT_BIOS_CMD_BASE | 0x05)
29*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_READ_PL1_SETTING (IPC_PUNIT_BIOS_CMD_BASE | 0x06)
30*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_WRITE_PL1_SETTING (IPC_PUNIT_BIOS_CMD_BASE | 0x07)
31*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_TRIGGER_VDD_RAM (IPC_PUNIT_BIOS_CMD_BASE | 0x08)
32*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_READ_TELE_INFO (IPC_PUNIT_BIOS_CMD_BASE | 0x09)
33*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_READ_TELE_TRACE_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x0a)
34*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_WRITE_TELE_TRACE_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x0b)
35*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_READ_TELE_EVENT_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x0c)
36*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_WRITE_TELE_EVENT_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x0d)
37*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_READ_TELE_TRACE (IPC_PUNIT_BIOS_CMD_BASE | 0x0e)
38*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_WRITE_TELE_TRACE (IPC_PUNIT_BIOS_CMD_BASE | 0x0f)
39*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_READ_TELE_EVENT (IPC_PUNIT_BIOS_CMD_BASE | 0x10)
40*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_WRITE_TELE_EVENT (IPC_PUNIT_BIOS_CMD_BASE | 0x11)
41*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_READ_MODULE_TEMP (IPC_PUNIT_BIOS_CMD_BASE | 0x12)
42*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_RESERVED (IPC_PUNIT_BIOS_CMD_BASE | 0x13)
43*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_READ_VOLTAGE_OVER (IPC_PUNIT_BIOS_CMD_BASE | 0x14)
44*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_WRITE_VOLTAGE_OVER (IPC_PUNIT_BIOS_CMD_BASE | 0x15)
45*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_READ_RATIO_OVER (IPC_PUNIT_BIOS_CMD_BASE | 0x16)
46*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_WRITE_RATIO_OVER (IPC_PUNIT_BIOS_CMD_BASE | 0x17)
47*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_READ_VF_GL_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x18)
48*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_WRITE_VF_GL_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x19)
49*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_READ_FM_SOC_TEMP_THRESH (IPC_PUNIT_BIOS_CMD_BASE | 0x1a)
50*4882a593Smuzhiyun #define IPC_PUNIT_BIOS_WRITE_FM_SOC_TEMP_THRESH (IPC_PUNIT_BIOS_CMD_BASE | 0x1b)
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* GT Driver => Pcode commands */
53*4882a593Smuzhiyun #define IPC_PUNIT_GTD_ZERO (IPC_PUNIT_GTD_CMD_BASE | 0x00)
54*4882a593Smuzhiyun #define IPC_PUNIT_GTD_CONFIG (IPC_PUNIT_GTD_CMD_BASE | 0x01)
55*4882a593Smuzhiyun #define IPC_PUNIT_GTD_READ_ICCP_LIC_CDYN_SCAL (IPC_PUNIT_GTD_CMD_BASE | 0x02)
56*4882a593Smuzhiyun #define IPC_PUNIT_GTD_WRITE_ICCP_LIC_CDYN_SCAL (IPC_PUNIT_GTD_CMD_BASE | 0x03)
57*4882a593Smuzhiyun #define IPC_PUNIT_GTD_GET_WM_VAL (IPC_PUNIT_GTD_CMD_BASE | 0x06)
58*4882a593Smuzhiyun #define IPC_PUNIT_GTD_WRITE_CONFIG_WISHREQ (IPC_PUNIT_GTD_CMD_BASE | 0x07)
59*4882a593Smuzhiyun #define IPC_PUNIT_GTD_READ_REQ_DUTY_CYCLE (IPC_PUNIT_GTD_CMD_BASE | 0x16)
60*4882a593Smuzhiyun #define IPC_PUNIT_GTD_DIS_VOL_FREQ_CHG_REQUEST (IPC_PUNIT_GTD_CMD_BASE | 0x17)
61*4882a593Smuzhiyun #define IPC_PUNIT_GTD_DYNA_DUTY_CYCLE_CTRL (IPC_PUNIT_GTD_CMD_BASE | 0x1a)
62*4882a593Smuzhiyun #define IPC_PUNIT_GTD_DYNA_DUTY_CYCLE_TUNING (IPC_PUNIT_GTD_CMD_BASE | 0x1c)
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* ISP Driver => Pcode commands */
65*4882a593Smuzhiyun #define IPC_PUNIT_ISPD_ZERO (IPC_PUNIT_ISPD_CMD_BASE | 0x00)
66*4882a593Smuzhiyun #define IPC_PUNIT_ISPD_CONFIG (IPC_PUNIT_ISPD_CMD_BASE | 0x01)
67*4882a593Smuzhiyun #define IPC_PUNIT_ISPD_GET_ISP_LTR_VAL (IPC_PUNIT_ISPD_CMD_BASE | 0x02)
68*4882a593Smuzhiyun #define IPC_PUNIT_ISPD_ACCESS_IU_FREQ_BOUNDS (IPC_PUNIT_ISPD_CMD_BASE | 0x03)
69*4882a593Smuzhiyun #define IPC_PUNIT_ISPD_READ_CDYN_LEVEL (IPC_PUNIT_ISPD_CMD_BASE | 0x04)
70*4882a593Smuzhiyun #define IPC_PUNIT_ISPD_WRITE_CDYN_LEVEL (IPC_PUNIT_ISPD_CMD_BASE | 0x05)
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Error codes */
73*4882a593Smuzhiyun #define IPC_PUNIT_ERR_SUCCESS 0
74*4882a593Smuzhiyun #define IPC_PUNIT_ERR_INVALID_CMD 1
75*4882a593Smuzhiyun #define IPC_PUNIT_ERR_INVALID_PARAMETER 2
76*4882a593Smuzhiyun #define IPC_PUNIT_ERR_CMD_TIMEOUT 3
77*4882a593Smuzhiyun #define IPC_PUNIT_ERR_CMD_LOCKED 4
78*4882a593Smuzhiyun #define IPC_PUNIT_ERR_INVALID_VR_ID 5
79*4882a593Smuzhiyun #define IPC_PUNIT_ERR_VR_ERR 6
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_INTEL_PUNIT_IPC)
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun int intel_punit_ipc_simple_command(int cmd, int para1, int para2);
84*4882a593Smuzhiyun int intel_punit_ipc_command(u32 cmd, u32 para1, u32 para2, u32 *in, u32 *out);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #else
87*4882a593Smuzhiyun
intel_punit_ipc_simple_command(int cmd,int para1,int para2)88*4882a593Smuzhiyun static inline int intel_punit_ipc_simple_command(int cmd,
89*4882a593Smuzhiyun int para1, int para2)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun return -ENODEV;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
intel_punit_ipc_command(u32 cmd,u32 para1,u32 para2,u32 * in,u32 * out)94*4882a593Smuzhiyun static inline int intel_punit_ipc_command(u32 cmd, u32 para1, u32 para2,
95*4882a593Smuzhiyun u32 *in, u32 *out)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun return -ENODEV;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun #endif /* CONFIG_INTEL_PUNIT_IPC */
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #endif
103