1*4882a593Smuzhiyun #ifndef _ASM_INTEL_DS_H 2*4882a593Smuzhiyun #define _ASM_INTEL_DS_H 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #include <linux/percpu-defs.h> 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #define BTS_BUFFER_SIZE (PAGE_SIZE << 4) 7*4882a593Smuzhiyun #define PEBS_BUFFER_SIZE (PAGE_SIZE << 4) 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* The maximal number of PEBS events: */ 10*4882a593Smuzhiyun #define MAX_PEBS_EVENTS 8 11*4882a593Smuzhiyun #define MAX_FIXED_PEBS_EVENTS 4 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * A debug store configuration. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * We only support architectures that use 64bit fields. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun struct debug_store { 19*4882a593Smuzhiyun u64 bts_buffer_base; 20*4882a593Smuzhiyun u64 bts_index; 21*4882a593Smuzhiyun u64 bts_absolute_maximum; 22*4882a593Smuzhiyun u64 bts_interrupt_threshold; 23*4882a593Smuzhiyun u64 pebs_buffer_base; 24*4882a593Smuzhiyun u64 pebs_index; 25*4882a593Smuzhiyun u64 pebs_absolute_maximum; 26*4882a593Smuzhiyun u64 pebs_interrupt_threshold; 27*4882a593Smuzhiyun u64 pebs_event_reset[MAX_PEBS_EVENTS + MAX_FIXED_PEBS_EVENTS]; 28*4882a593Smuzhiyun } __aligned(PAGE_SIZE); 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun DECLARE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store); 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun struct debug_store_buffers { 33*4882a593Smuzhiyun char bts_buffer[BTS_BUFFER_SIZE]; 34*4882a593Smuzhiyun char pebs_buffer[PEBS_BUFFER_SIZE]; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #endif 38