1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * intel-mid.h: Intel MID specific setup code
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (C) Copyright 2009 Intel Corporation
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #ifndef _ASM_X86_INTEL_MID_H
8*4882a593Smuzhiyun #define _ASM_X86_INTEL_MID_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/sfi.h>
11*4882a593Smuzhiyun #include <linux/pci.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun extern int intel_mid_pci_init(void);
15*4882a593Smuzhiyun extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
16*4882a593Smuzhiyun extern pci_power_t intel_mid_pci_get_power_state(struct pci_dev *pdev);
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun extern void intel_mid_pwr_power_off(void);
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define INTEL_MID_PWR_LSS_OFFSET 4
21*4882a593Smuzhiyun #define INTEL_MID_PWR_LSS_TYPE (1 << 7)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev);
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun extern int get_gpio_by_name(const char *name);
26*4882a593Smuzhiyun extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
27*4882a593Smuzhiyun extern int __init sfi_parse_mtmr(struct sfi_table_header *table);
28*4882a593Smuzhiyun extern int sfi_mrtc_num;
29*4882a593Smuzhiyun extern struct sfi_rtc_table_entry sfi_mrtc_array[];
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * Here defines the array of devices platform data that IAFW would export
33*4882a593Smuzhiyun * through SFI "DEVS" table, we use name and type to match the device and
34*4882a593Smuzhiyun * its platform data.
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun struct devs_id {
37*4882a593Smuzhiyun char name[SFI_NAME_LEN + 1];
38*4882a593Smuzhiyun u8 type;
39*4882a593Smuzhiyun u8 delay;
40*4882a593Smuzhiyun u8 msic;
41*4882a593Smuzhiyun void *(*get_platform_data)(void *info);
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define sfi_device(i) \
45*4882a593Smuzhiyun static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \
46*4882a593Smuzhiyun __section(".x86_intel_mid_dev.init") = &i
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /**
49*4882a593Smuzhiyun * struct mid_sd_board_info - template for SD device creation
50*4882a593Smuzhiyun * @name: identifies the driver
51*4882a593Smuzhiyun * @bus_num: board-specific identifier for a given SD controller
52*4882a593Smuzhiyun * @max_clk: the maximum frequency device supports
53*4882a593Smuzhiyun * @platform_data: the particular data stored there is driver-specific
54*4882a593Smuzhiyun */
55*4882a593Smuzhiyun struct mid_sd_board_info {
56*4882a593Smuzhiyun char name[SFI_NAME_LEN];
57*4882a593Smuzhiyun int bus_num;
58*4882a593Smuzhiyun unsigned short addr;
59*4882a593Smuzhiyun u32 max_clk;
60*4882a593Smuzhiyun void *platform_data;
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun * Medfield is the follow-up of Moorestown, it combines two chip solution into
65*4882a593Smuzhiyun * one. Other than that it also added always-on and constant tsc and lapic
66*4882a593Smuzhiyun * timers. Medfield is the platform name, and the chip name is called Penwell
67*4882a593Smuzhiyun * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
68*4882a593Smuzhiyun * identified via MSRs.
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun enum intel_mid_cpu_type {
71*4882a593Smuzhiyun /* 1 was Moorestown */
72*4882a593Smuzhiyun INTEL_MID_CPU_CHIP_PENWELL = 2,
73*4882a593Smuzhiyun INTEL_MID_CPU_CHIP_CLOVERVIEW,
74*4882a593Smuzhiyun INTEL_MID_CPU_CHIP_TANGIER,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun extern enum intel_mid_cpu_type __intel_mid_cpu_chip;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #ifdef CONFIG_X86_INTEL_MID
80*4882a593Smuzhiyun
intel_mid_identify_cpu(void)81*4882a593Smuzhiyun static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun return __intel_mid_cpu_chip;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
intel_mid_has_msic(void)86*4882a593Smuzhiyun static inline bool intel_mid_has_msic(void)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun extern void intel_scu_devices_create(void);
92*4882a593Smuzhiyun extern void intel_scu_devices_destroy(void);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun #else /* !CONFIG_X86_INTEL_MID */
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun #define intel_mid_identify_cpu() 0
97*4882a593Smuzhiyun #define intel_mid_has_msic() 0
98*4882a593Smuzhiyun
intel_scu_devices_create(void)99*4882a593Smuzhiyun static inline void intel_scu_devices_create(void) { }
intel_scu_devices_destroy(void)100*4882a593Smuzhiyun static inline void intel_scu_devices_destroy(void) { }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #endif /* !CONFIG_X86_INTEL_MID */
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun enum intel_mid_timer_options {
105*4882a593Smuzhiyun INTEL_MID_TIMER_DEFAULT,
106*4882a593Smuzhiyun INTEL_MID_TIMER_APBT_ONLY,
107*4882a593Smuzhiyun INTEL_MID_TIMER_LAPIC_APBT,
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun extern enum intel_mid_timer_options intel_mid_timer_options;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* Bus Select SoC Fuse value */
113*4882a593Smuzhiyun #define BSEL_SOC_FUSE_MASK 0x7
114*4882a593Smuzhiyun /* FSB 133MHz */
115*4882a593Smuzhiyun #define BSEL_SOC_FUSE_001 0x1
116*4882a593Smuzhiyun /* FSB 100MHz */
117*4882a593Smuzhiyun #define BSEL_SOC_FUSE_101 0x5
118*4882a593Smuzhiyun /* FSB 83MHz */
119*4882a593Smuzhiyun #define BSEL_SOC_FUSE_111 0x7
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun #define SFI_MTMR_MAX_NUM 8
122*4882a593Smuzhiyun #define SFI_MRTC_MAX 8
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* VRTC timer */
125*4882a593Smuzhiyun #define MRST_VRTC_MAP_SZ 1024
126*4882a593Smuzhiyun /* #define MRST_VRTC_PGOFFSET 0xc00 */
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun extern void intel_mid_rtc_init(void);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /* The offset for the mapping of global gpio pin to irq */
131*4882a593Smuzhiyun #define INTEL_MID_IRQ_OFFSET 0x100
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun #endif /* _ASM_X86_INTEL_MID_H */
134