1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Generate .byte code for some instructions not supported by old 4*4882a593Smuzhiyun * binutils. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef X86_ASM_INST_H 7*4882a593Smuzhiyun #define X86_ASM_INST_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifdef __ASSEMBLY__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define REG_NUM_INVALID 100 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define REG_TYPE_R32 0 14*4882a593Smuzhiyun #define REG_TYPE_R64 1 15*4882a593Smuzhiyun #define REG_TYPE_INVALID 100 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun .macro R32_NUM opd r32 18*4882a593Smuzhiyun \opd = REG_NUM_INVALID 19*4882a593Smuzhiyun .ifc \r32,%eax 20*4882a593Smuzhiyun \opd = 0 21*4882a593Smuzhiyun .endif 22*4882a593Smuzhiyun .ifc \r32,%ecx 23*4882a593Smuzhiyun \opd = 1 24*4882a593Smuzhiyun .endif 25*4882a593Smuzhiyun .ifc \r32,%edx 26*4882a593Smuzhiyun \opd = 2 27*4882a593Smuzhiyun .endif 28*4882a593Smuzhiyun .ifc \r32,%ebx 29*4882a593Smuzhiyun \opd = 3 30*4882a593Smuzhiyun .endif 31*4882a593Smuzhiyun .ifc \r32,%esp 32*4882a593Smuzhiyun \opd = 4 33*4882a593Smuzhiyun .endif 34*4882a593Smuzhiyun .ifc \r32,%ebp 35*4882a593Smuzhiyun \opd = 5 36*4882a593Smuzhiyun .endif 37*4882a593Smuzhiyun .ifc \r32,%esi 38*4882a593Smuzhiyun \opd = 6 39*4882a593Smuzhiyun .endif 40*4882a593Smuzhiyun .ifc \r32,%edi 41*4882a593Smuzhiyun \opd = 7 42*4882a593Smuzhiyun .endif 43*4882a593Smuzhiyun #ifdef CONFIG_X86_64 44*4882a593Smuzhiyun .ifc \r32,%r8d 45*4882a593Smuzhiyun \opd = 8 46*4882a593Smuzhiyun .endif 47*4882a593Smuzhiyun .ifc \r32,%r9d 48*4882a593Smuzhiyun \opd = 9 49*4882a593Smuzhiyun .endif 50*4882a593Smuzhiyun .ifc \r32,%r10d 51*4882a593Smuzhiyun \opd = 10 52*4882a593Smuzhiyun .endif 53*4882a593Smuzhiyun .ifc \r32,%r11d 54*4882a593Smuzhiyun \opd = 11 55*4882a593Smuzhiyun .endif 56*4882a593Smuzhiyun .ifc \r32,%r12d 57*4882a593Smuzhiyun \opd = 12 58*4882a593Smuzhiyun .endif 59*4882a593Smuzhiyun .ifc \r32,%r13d 60*4882a593Smuzhiyun \opd = 13 61*4882a593Smuzhiyun .endif 62*4882a593Smuzhiyun .ifc \r32,%r14d 63*4882a593Smuzhiyun \opd = 14 64*4882a593Smuzhiyun .endif 65*4882a593Smuzhiyun .ifc \r32,%r15d 66*4882a593Smuzhiyun \opd = 15 67*4882a593Smuzhiyun .endif 68*4882a593Smuzhiyun #endif 69*4882a593Smuzhiyun .endm 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun .macro R64_NUM opd r64 72*4882a593Smuzhiyun \opd = REG_NUM_INVALID 73*4882a593Smuzhiyun #ifdef CONFIG_X86_64 74*4882a593Smuzhiyun .ifc \r64,%rax 75*4882a593Smuzhiyun \opd = 0 76*4882a593Smuzhiyun .endif 77*4882a593Smuzhiyun .ifc \r64,%rcx 78*4882a593Smuzhiyun \opd = 1 79*4882a593Smuzhiyun .endif 80*4882a593Smuzhiyun .ifc \r64,%rdx 81*4882a593Smuzhiyun \opd = 2 82*4882a593Smuzhiyun .endif 83*4882a593Smuzhiyun .ifc \r64,%rbx 84*4882a593Smuzhiyun \opd = 3 85*4882a593Smuzhiyun .endif 86*4882a593Smuzhiyun .ifc \r64,%rsp 87*4882a593Smuzhiyun \opd = 4 88*4882a593Smuzhiyun .endif 89*4882a593Smuzhiyun .ifc \r64,%rbp 90*4882a593Smuzhiyun \opd = 5 91*4882a593Smuzhiyun .endif 92*4882a593Smuzhiyun .ifc \r64,%rsi 93*4882a593Smuzhiyun \opd = 6 94*4882a593Smuzhiyun .endif 95*4882a593Smuzhiyun .ifc \r64,%rdi 96*4882a593Smuzhiyun \opd = 7 97*4882a593Smuzhiyun .endif 98*4882a593Smuzhiyun .ifc \r64,%r8 99*4882a593Smuzhiyun \opd = 8 100*4882a593Smuzhiyun .endif 101*4882a593Smuzhiyun .ifc \r64,%r9 102*4882a593Smuzhiyun \opd = 9 103*4882a593Smuzhiyun .endif 104*4882a593Smuzhiyun .ifc \r64,%r10 105*4882a593Smuzhiyun \opd = 10 106*4882a593Smuzhiyun .endif 107*4882a593Smuzhiyun .ifc \r64,%r11 108*4882a593Smuzhiyun \opd = 11 109*4882a593Smuzhiyun .endif 110*4882a593Smuzhiyun .ifc \r64,%r12 111*4882a593Smuzhiyun \opd = 12 112*4882a593Smuzhiyun .endif 113*4882a593Smuzhiyun .ifc \r64,%r13 114*4882a593Smuzhiyun \opd = 13 115*4882a593Smuzhiyun .endif 116*4882a593Smuzhiyun .ifc \r64,%r14 117*4882a593Smuzhiyun \opd = 14 118*4882a593Smuzhiyun .endif 119*4882a593Smuzhiyun .ifc \r64,%r15 120*4882a593Smuzhiyun \opd = 15 121*4882a593Smuzhiyun .endif 122*4882a593Smuzhiyun #endif 123*4882a593Smuzhiyun .endm 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun .macro REG_TYPE type reg 126*4882a593Smuzhiyun R32_NUM reg_type_r32 \reg 127*4882a593Smuzhiyun R64_NUM reg_type_r64 \reg 128*4882a593Smuzhiyun .if reg_type_r64 <> REG_NUM_INVALID 129*4882a593Smuzhiyun \type = REG_TYPE_R64 130*4882a593Smuzhiyun .elseif reg_type_r32 <> REG_NUM_INVALID 131*4882a593Smuzhiyun \type = REG_TYPE_R32 132*4882a593Smuzhiyun .else 133*4882a593Smuzhiyun \type = REG_TYPE_INVALID 134*4882a593Smuzhiyun .endif 135*4882a593Smuzhiyun .endm 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun .macro PFX_REX opd1 opd2 W=0 138*4882a593Smuzhiyun .if ((\opd1 | \opd2) & 8) || \W 139*4882a593Smuzhiyun .byte 0x40 | ((\opd1 & 8) >> 3) | ((\opd2 & 8) >> 1) | (\W << 3) 140*4882a593Smuzhiyun .endif 141*4882a593Smuzhiyun .endm 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun .macro MODRM mod opd1 opd2 144*4882a593Smuzhiyun .byte \mod | (\opd1 & 7) | ((\opd2 & 7) << 3) 145*4882a593Smuzhiyun .endm 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun .macro RDPID opd 148*4882a593Smuzhiyun REG_TYPE rdpid_opd_type \opd 149*4882a593Smuzhiyun .if rdpid_opd_type == REG_TYPE_R64 150*4882a593Smuzhiyun R64_NUM rdpid_opd \opd 151*4882a593Smuzhiyun .else 152*4882a593Smuzhiyun R32_NUM rdpid_opd \opd 153*4882a593Smuzhiyun .endif 154*4882a593Smuzhiyun .byte 0xf3 155*4882a593Smuzhiyun .if rdpid_opd > 7 156*4882a593Smuzhiyun PFX_REX rdpid_opd 0 157*4882a593Smuzhiyun .endif 158*4882a593Smuzhiyun .byte 0x0f, 0xc7 159*4882a593Smuzhiyun MODRM 0xc0 rdpid_opd 0x7 160*4882a593Smuzhiyun .endm 161*4882a593Smuzhiyun #endif 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun #endif 164