1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _ASM_X86_I8259_H 3*4882a593Smuzhiyun #define _ASM_X86_I8259_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/delay.h> 6*4882a593Smuzhiyun #include <asm/io.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun extern unsigned int cached_irq_mask; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define __byte(x, y) (((unsigned char *)&(y))[x]) 11*4882a593Smuzhiyun #define cached_master_mask (__byte(0, cached_irq_mask)) 12*4882a593Smuzhiyun #define cached_slave_mask (__byte(1, cached_irq_mask)) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* i8259A PIC registers */ 15*4882a593Smuzhiyun #define PIC_MASTER_CMD 0x20 16*4882a593Smuzhiyun #define PIC_MASTER_IMR 0x21 17*4882a593Smuzhiyun #define PIC_MASTER_ISR PIC_MASTER_CMD 18*4882a593Smuzhiyun #define PIC_MASTER_POLL PIC_MASTER_ISR 19*4882a593Smuzhiyun #define PIC_MASTER_OCW3 PIC_MASTER_ISR 20*4882a593Smuzhiyun #define PIC_SLAVE_CMD 0xa0 21*4882a593Smuzhiyun #define PIC_SLAVE_IMR 0xa1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* i8259A PIC related value */ 24*4882a593Smuzhiyun #define PIC_CASCADE_IR 2 25*4882a593Smuzhiyun #define MASTER_ICW4_DEFAULT 0x01 26*4882a593Smuzhiyun #define SLAVE_ICW4_DEFAULT 0x01 27*4882a593Smuzhiyun #define PIC_ICW4_AEOI 2 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun extern raw_spinlock_t i8259A_lock; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* the PIC may need a careful delay on some platforms, hence specific calls */ inb_pic(unsigned int port)32*4882a593Smuzhiyunstatic inline unsigned char inb_pic(unsigned int port) 33*4882a593Smuzhiyun { 34*4882a593Smuzhiyun unsigned char value = inb(port); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* 37*4882a593Smuzhiyun * delay for some accesses to PIC on motherboard or in chipset 38*4882a593Smuzhiyun * must be at least one microsecond, so be safe here: 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun udelay(2); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun return value; 43*4882a593Smuzhiyun } 44*4882a593Smuzhiyun outb_pic(unsigned char value,unsigned int port)45*4882a593Smuzhiyunstatic inline void outb_pic(unsigned char value, unsigned int port) 46*4882a593Smuzhiyun { 47*4882a593Smuzhiyun outb(value, port); 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * delay for some accesses to PIC on motherboard or in chipset 50*4882a593Smuzhiyun * must be at least one microsecond, so be safe here: 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun udelay(2); 53*4882a593Smuzhiyun } 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun extern struct irq_chip i8259A_chip; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct legacy_pic { 58*4882a593Smuzhiyun int nr_legacy_irqs; 59*4882a593Smuzhiyun struct irq_chip *chip; 60*4882a593Smuzhiyun void (*mask)(unsigned int irq); 61*4882a593Smuzhiyun void (*unmask)(unsigned int irq); 62*4882a593Smuzhiyun void (*mask_all)(void); 63*4882a593Smuzhiyun void (*restore_mask)(void); 64*4882a593Smuzhiyun void (*init)(int auto_eoi); 65*4882a593Smuzhiyun int (*probe)(void); 66*4882a593Smuzhiyun int (*irq_pending)(unsigned int irq); 67*4882a593Smuzhiyun void (*make_irq)(unsigned int irq); 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun extern struct legacy_pic *legacy_pic; 71*4882a593Smuzhiyun extern struct legacy_pic null_legacy_pic; 72*4882a593Smuzhiyun has_legacy_pic(void)73*4882a593Smuzhiyunstatic inline bool has_legacy_pic(void) 74*4882a593Smuzhiyun { 75*4882a593Smuzhiyun return legacy_pic != &null_legacy_pic; 76*4882a593Smuzhiyun } 77*4882a593Smuzhiyun nr_legacy_irqs(void)78*4882a593Smuzhiyunstatic inline int nr_legacy_irqs(void) 79*4882a593Smuzhiyun { 80*4882a593Smuzhiyun return legacy_pic->nr_legacy_irqs; 81*4882a593Smuzhiyun } 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #endif /* _ASM_X86_I8259_H */ 84