1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef _ASM_X86_HW_IRQ_H
3*4882a593Smuzhiyun #define _ASM_X86_HW_IRQ_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun /*
6*4882a593Smuzhiyun * (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * moved some of the old arch/i386/kernel/irq.h to here. VY
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * IRQ/IPI changes taken from work by Thomas Radke
11*4882a593Smuzhiyun * <tomsoft@informatik.tu-chemnitz.de>
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * hacked by Andi Kleen for x86-64.
14*4882a593Smuzhiyun * unified by tglx
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <asm/irq_vectors.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define IRQ_MATRIX_BITS NR_VECTORS
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #ifndef __ASSEMBLY__
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <linux/percpu.h>
24*4882a593Smuzhiyun #include <linux/profile.h>
25*4882a593Smuzhiyun #include <linux/smp.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <linux/atomic.h>
28*4882a593Smuzhiyun #include <asm/irq.h>
29*4882a593Smuzhiyun #include <asm/sections.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #ifdef CONFIG_X86_LOCAL_APIC
32*4882a593Smuzhiyun struct irq_data;
33*4882a593Smuzhiyun struct pci_dev;
34*4882a593Smuzhiyun struct msi_desc;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun enum irq_alloc_type {
37*4882a593Smuzhiyun X86_IRQ_ALLOC_TYPE_IOAPIC = 1,
38*4882a593Smuzhiyun X86_IRQ_ALLOC_TYPE_HPET,
39*4882a593Smuzhiyun X86_IRQ_ALLOC_TYPE_PCI_MSI,
40*4882a593Smuzhiyun X86_IRQ_ALLOC_TYPE_PCI_MSIX,
41*4882a593Smuzhiyun X86_IRQ_ALLOC_TYPE_DMAR,
42*4882a593Smuzhiyun X86_IRQ_ALLOC_TYPE_UV,
43*4882a593Smuzhiyun X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT,
44*4882a593Smuzhiyun X86_IRQ_ALLOC_TYPE_HPET_GET_PARENT,
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun struct ioapic_alloc_info {
48*4882a593Smuzhiyun int pin;
49*4882a593Smuzhiyun int node;
50*4882a593Smuzhiyun u32 trigger : 1;
51*4882a593Smuzhiyun u32 polarity : 1;
52*4882a593Smuzhiyun u32 valid : 1;
53*4882a593Smuzhiyun struct IO_APIC_route_entry *entry;
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun struct uv_alloc_info {
57*4882a593Smuzhiyun int limit;
58*4882a593Smuzhiyun int blade;
59*4882a593Smuzhiyun unsigned long offset;
60*4882a593Smuzhiyun char *name;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /**
65*4882a593Smuzhiyun * irq_alloc_info - X86 specific interrupt allocation info
66*4882a593Smuzhiyun * @type: X86 specific allocation type
67*4882a593Smuzhiyun * @flags: Flags for allocation tweaks
68*4882a593Smuzhiyun * @devid: Device ID for allocations
69*4882a593Smuzhiyun * @hwirq: Associated hw interrupt number in the domain
70*4882a593Smuzhiyun * @mask: CPU mask for vector allocation
71*4882a593Smuzhiyun * @desc: Pointer to msi descriptor
72*4882a593Smuzhiyun * @data: Allocation specific data
73*4882a593Smuzhiyun *
74*4882a593Smuzhiyun * @ioapic: IOAPIC specific allocation data
75*4882a593Smuzhiyun * @uv: UV specific allocation data
76*4882a593Smuzhiyun */
77*4882a593Smuzhiyun struct irq_alloc_info {
78*4882a593Smuzhiyun enum irq_alloc_type type;
79*4882a593Smuzhiyun u32 flags;
80*4882a593Smuzhiyun u32 devid;
81*4882a593Smuzhiyun irq_hw_number_t hwirq;
82*4882a593Smuzhiyun const struct cpumask *mask;
83*4882a593Smuzhiyun struct msi_desc *desc;
84*4882a593Smuzhiyun void *data;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun union {
87*4882a593Smuzhiyun struct ioapic_alloc_info ioapic;
88*4882a593Smuzhiyun struct uv_alloc_info uv;
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun struct irq_cfg {
93*4882a593Smuzhiyun unsigned int dest_apicid;
94*4882a593Smuzhiyun unsigned int vector;
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun extern struct irq_cfg *irq_cfg(unsigned int irq);
98*4882a593Smuzhiyun extern struct irq_cfg *irqd_cfg(struct irq_data *irq_data);
99*4882a593Smuzhiyun extern void lock_vector_lock(void);
100*4882a593Smuzhiyun extern void unlock_vector_lock(void);
101*4882a593Smuzhiyun #ifdef CONFIG_SMP
102*4882a593Smuzhiyun extern void send_cleanup_vector(struct irq_cfg *);
103*4882a593Smuzhiyun extern void irq_complete_move(struct irq_cfg *cfg);
104*4882a593Smuzhiyun #else
send_cleanup_vector(struct irq_cfg * c)105*4882a593Smuzhiyun static inline void send_cleanup_vector(struct irq_cfg *c) { }
irq_complete_move(struct irq_cfg * c)106*4882a593Smuzhiyun static inline void irq_complete_move(struct irq_cfg *c) { }
107*4882a593Smuzhiyun #endif
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun extern void apic_ack_edge(struct irq_data *data);
110*4882a593Smuzhiyun #else /* CONFIG_X86_LOCAL_APIC */
lock_vector_lock(void)111*4882a593Smuzhiyun static inline void lock_vector_lock(void) {}
unlock_vector_lock(void)112*4882a593Smuzhiyun static inline void unlock_vector_lock(void) {}
113*4882a593Smuzhiyun #endif /* CONFIG_X86_LOCAL_APIC */
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /* Statistics */
116*4882a593Smuzhiyun extern atomic_t irq_err_count;
117*4882a593Smuzhiyun extern atomic_t irq_mis_count;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun extern void elcr_set_level_irq(unsigned int irq);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun extern char irq_entries_start[];
122*4882a593Smuzhiyun #ifdef CONFIG_TRACING
123*4882a593Smuzhiyun #define trace_irq_entries_start irq_entries_start
124*4882a593Smuzhiyun #endif
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun extern char spurious_entries_start[];
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun #define VECTOR_UNUSED NULL
129*4882a593Smuzhiyun #define VECTOR_SHUTDOWN ((void *)-1L)
130*4882a593Smuzhiyun #define VECTOR_RETRIGGERED ((void *)-2L)
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun typedef struct irq_desc* vector_irq_t[NR_VECTORS];
133*4882a593Smuzhiyun DECLARE_PER_CPU(vector_irq_t, vector_irq);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun #endif /* !ASSEMBLY_ */
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun #endif /* _ASM_X86_HW_IRQ_H */
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