1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _ASM_X86_HPET_H 3*4882a593Smuzhiyun #define _ASM_X86_HPET_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/msi.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifdef CONFIG_HPET_TIMER 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define HPET_MMAP_SIZE 1024 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define HPET_ID 0x000 12*4882a593Smuzhiyun #define HPET_PERIOD 0x004 13*4882a593Smuzhiyun #define HPET_CFG 0x010 14*4882a593Smuzhiyun #define HPET_STATUS 0x020 15*4882a593Smuzhiyun #define HPET_COUNTER 0x0f0 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define HPET_Tn_CFG(n) (0x100 + 0x20 * n) 18*4882a593Smuzhiyun #define HPET_Tn_CMP(n) (0x108 + 0x20 * n) 19*4882a593Smuzhiyun #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define HPET_T0_CFG 0x100 22*4882a593Smuzhiyun #define HPET_T0_CMP 0x108 23*4882a593Smuzhiyun #define HPET_T0_ROUTE 0x110 24*4882a593Smuzhiyun #define HPET_T1_CFG 0x120 25*4882a593Smuzhiyun #define HPET_T1_CMP 0x128 26*4882a593Smuzhiyun #define HPET_T1_ROUTE 0x130 27*4882a593Smuzhiyun #define HPET_T2_CFG 0x140 28*4882a593Smuzhiyun #define HPET_T2_CMP 0x148 29*4882a593Smuzhiyun #define HPET_T2_ROUTE 0x150 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define HPET_ID_REV 0x000000ff 32*4882a593Smuzhiyun #define HPET_ID_NUMBER 0x00001f00 33*4882a593Smuzhiyun #define HPET_ID_64BIT 0x00002000 34*4882a593Smuzhiyun #define HPET_ID_LEGSUP 0x00008000 35*4882a593Smuzhiyun #define HPET_ID_VENDOR 0xffff0000 36*4882a593Smuzhiyun #define HPET_ID_NUMBER_SHIFT 8 37*4882a593Smuzhiyun #define HPET_ID_VENDOR_SHIFT 16 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define HPET_CFG_ENABLE 0x001 40*4882a593Smuzhiyun #define HPET_CFG_LEGACY 0x002 41*4882a593Smuzhiyun #define HPET_LEGACY_8254 2 42*4882a593Smuzhiyun #define HPET_LEGACY_RTC 8 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define HPET_TN_LEVEL 0x0002 45*4882a593Smuzhiyun #define HPET_TN_ENABLE 0x0004 46*4882a593Smuzhiyun #define HPET_TN_PERIODIC 0x0008 47*4882a593Smuzhiyun #define HPET_TN_PERIODIC_CAP 0x0010 48*4882a593Smuzhiyun #define HPET_TN_64BIT_CAP 0x0020 49*4882a593Smuzhiyun #define HPET_TN_SETVAL 0x0040 50*4882a593Smuzhiyun #define HPET_TN_32BIT 0x0100 51*4882a593Smuzhiyun #define HPET_TN_ROUTE 0x3e00 52*4882a593Smuzhiyun #define HPET_TN_FSB 0x4000 53*4882a593Smuzhiyun #define HPET_TN_FSB_CAP 0x8000 54*4882a593Smuzhiyun #define HPET_TN_ROUTE_SHIFT 9 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Max HPET Period is 10^8 femto sec as in HPET spec */ 57*4882a593Smuzhiyun #define HPET_MAX_PERIOD 100000000UL 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * Min HPET period is 10^5 femto sec just for safety. If it is less than this, 60*4882a593Smuzhiyun * then 32 bit HPET counter wrapsaround in less than 0.5 sec. 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun #define HPET_MIN_PERIOD 100000UL 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* hpet memory map physical address */ 65*4882a593Smuzhiyun extern unsigned long hpet_address; 66*4882a593Smuzhiyun extern unsigned long force_hpet_address; 67*4882a593Smuzhiyun extern bool boot_hpet_disable; 68*4882a593Smuzhiyun extern u8 hpet_blockid; 69*4882a593Smuzhiyun extern bool hpet_force_user; 70*4882a593Smuzhiyun extern bool hpet_msi_disable; 71*4882a593Smuzhiyun extern int is_hpet_enabled(void); 72*4882a593Smuzhiyun extern int hpet_enable(void); 73*4882a593Smuzhiyun extern void hpet_disable(void); 74*4882a593Smuzhiyun extern unsigned int hpet_readl(unsigned int a); 75*4882a593Smuzhiyun extern void force_hpet_resume(void); 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun struct irq_data; 78*4882a593Smuzhiyun struct hpet_channel; 79*4882a593Smuzhiyun struct irq_domain; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun extern void hpet_msi_unmask(struct irq_data *data); 82*4882a593Smuzhiyun extern void hpet_msi_mask(struct irq_data *data); 83*4882a593Smuzhiyun extern void hpet_msi_write(struct hpet_channel *hc, struct msi_msg *msg); 84*4882a593Smuzhiyun extern struct irq_domain *hpet_create_irq_domain(int hpet_id); 85*4882a593Smuzhiyun extern int hpet_assign_irq(struct irq_domain *domain, 86*4882a593Smuzhiyun struct hpet_channel *hc, int dev_num); 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #ifdef CONFIG_HPET_EMULATE_RTC 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #include <linux/interrupt.h> 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun typedef irqreturn_t (*rtc_irq_handler)(int interrupt, void *cookie); 93*4882a593Smuzhiyun extern int hpet_mask_rtc_irq_bit(unsigned long bit_mask); 94*4882a593Smuzhiyun extern int hpet_set_rtc_irq_bit(unsigned long bit_mask); 95*4882a593Smuzhiyun extern int hpet_set_alarm_time(unsigned char hrs, unsigned char min, 96*4882a593Smuzhiyun unsigned char sec); 97*4882a593Smuzhiyun extern int hpet_set_periodic_freq(unsigned long freq); 98*4882a593Smuzhiyun extern int hpet_rtc_dropped_irq(void); 99*4882a593Smuzhiyun extern int hpet_rtc_timer_init(void); 100*4882a593Smuzhiyun extern irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id); 101*4882a593Smuzhiyun extern int hpet_register_irq_handler(rtc_irq_handler handler); 102*4882a593Smuzhiyun extern void hpet_unregister_irq_handler(rtc_irq_handler handler); 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #endif /* CONFIG_HPET_EMULATE_RTC */ 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #else /* CONFIG_HPET_TIMER */ 107*4882a593Smuzhiyun hpet_enable(void)108*4882a593Smuzhiyunstatic inline int hpet_enable(void) { return 0; } is_hpet_enabled(void)109*4882a593Smuzhiyunstatic inline int is_hpet_enabled(void) { return 0; } 110*4882a593Smuzhiyun #define hpet_readl(a) 0 111*4882a593Smuzhiyun #define default_setup_hpet_msi NULL 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #endif 114*4882a593Smuzhiyun #endif /* _ASM_X86_HPET_H */ 115