1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Intel(R) Processor Trace PMU driver for perf
4*4882a593Smuzhiyun * Copyright (c) 2013-2014, Intel Corporation.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Intel PT is specified in the Intel Architecture Instruction Set Extensions
7*4882a593Smuzhiyun * Programming Reference:
8*4882a593Smuzhiyun * http://software.intel.com/en-us/intel-isa-extensions
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #ifndef __INTEL_PT_H__
12*4882a593Smuzhiyun #define __INTEL_PT_H__
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /*
15*4882a593Smuzhiyun * Single-entry ToPA: when this close to region boundary, switch
16*4882a593Smuzhiyun * buffers to avoid losing data.
17*4882a593Smuzhiyun */
18*4882a593Smuzhiyun #define TOPA_PMI_MARGIN 512
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define TOPA_SHIFT 12
21*4882a593Smuzhiyun
sizes(unsigned int tsz)22*4882a593Smuzhiyun static inline unsigned int sizes(unsigned int tsz)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun return 1 << (tsz + TOPA_SHIFT);
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct topa_entry {
28*4882a593Smuzhiyun u64 end : 1;
29*4882a593Smuzhiyun u64 rsvd0 : 1;
30*4882a593Smuzhiyun u64 intr : 1;
31*4882a593Smuzhiyun u64 rsvd1 : 1;
32*4882a593Smuzhiyun u64 stop : 1;
33*4882a593Smuzhiyun u64 rsvd2 : 1;
34*4882a593Smuzhiyun u64 size : 4;
35*4882a593Smuzhiyun u64 rsvd3 : 2;
36*4882a593Smuzhiyun u64 base : 36;
37*4882a593Smuzhiyun u64 rsvd4 : 16;
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* TSC to Core Crystal Clock Ratio */
41*4882a593Smuzhiyun #define CPUID_TSC_LEAF 0x15
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun struct pt_pmu {
44*4882a593Smuzhiyun struct pmu pmu;
45*4882a593Smuzhiyun u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
46*4882a593Smuzhiyun bool vmx;
47*4882a593Smuzhiyun bool branch_en_always_on;
48*4882a593Smuzhiyun unsigned long max_nonturbo_ratio;
49*4882a593Smuzhiyun unsigned int tsc_art_num;
50*4882a593Smuzhiyun unsigned int tsc_art_den;
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /**
54*4882a593Smuzhiyun * struct pt_buffer - buffer configuration; one buffer per task_struct or
55*4882a593Smuzhiyun * cpu, depending on perf event configuration
56*4882a593Smuzhiyun * @tables: list of ToPA tables in this buffer
57*4882a593Smuzhiyun * @first: shorthand for first topa table
58*4882a593Smuzhiyun * @last: shorthand for last topa table
59*4882a593Smuzhiyun * @cur: current topa table
60*4882a593Smuzhiyun * @nr_pages: buffer size in pages
61*4882a593Smuzhiyun * @cur_idx: current output region's index within @cur table
62*4882a593Smuzhiyun * @output_off: offset within the current output region
63*4882a593Smuzhiyun * @data_size: running total of the amount of data in this buffer
64*4882a593Smuzhiyun * @lost: if data was lost/truncated
65*4882a593Smuzhiyun * @head: logical write offset inside the buffer
66*4882a593Smuzhiyun * @snapshot: if this is for a snapshot/overwrite counter
67*4882a593Smuzhiyun * @single: use Single Range Output instead of ToPA
68*4882a593Smuzhiyun * @stop_pos: STOP topa entry index
69*4882a593Smuzhiyun * @intr_pos: INT topa entry index
70*4882a593Smuzhiyun * @stop_te: STOP topa entry pointer
71*4882a593Smuzhiyun * @intr_te: INT topa entry pointer
72*4882a593Smuzhiyun * @data_pages: array of pages from perf
73*4882a593Smuzhiyun * @topa_index: table of topa entries indexed by page offset
74*4882a593Smuzhiyun */
75*4882a593Smuzhiyun struct pt_buffer {
76*4882a593Smuzhiyun struct list_head tables;
77*4882a593Smuzhiyun struct topa *first, *last, *cur;
78*4882a593Smuzhiyun unsigned int cur_idx;
79*4882a593Smuzhiyun size_t output_off;
80*4882a593Smuzhiyun unsigned long nr_pages;
81*4882a593Smuzhiyun local_t data_size;
82*4882a593Smuzhiyun local64_t head;
83*4882a593Smuzhiyun bool snapshot;
84*4882a593Smuzhiyun bool single;
85*4882a593Smuzhiyun long stop_pos, intr_pos;
86*4882a593Smuzhiyun struct topa_entry *stop_te, *intr_te;
87*4882a593Smuzhiyun void **data_pages;
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun #define PT_FILTERS_NUM 4
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /**
93*4882a593Smuzhiyun * struct pt_filter - IP range filter configuration
94*4882a593Smuzhiyun * @msr_a: range start, goes to RTIT_ADDRn_A
95*4882a593Smuzhiyun * @msr_b: range end, goes to RTIT_ADDRn_B
96*4882a593Smuzhiyun * @config: 4-bit field in RTIT_CTL
97*4882a593Smuzhiyun */
98*4882a593Smuzhiyun struct pt_filter {
99*4882a593Smuzhiyun unsigned long msr_a;
100*4882a593Smuzhiyun unsigned long msr_b;
101*4882a593Smuzhiyun unsigned long config;
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /**
105*4882a593Smuzhiyun * struct pt_filters - IP range filtering context
106*4882a593Smuzhiyun * @filter: filters defined for this context
107*4882a593Smuzhiyun * @nr_filters: number of defined filters in the @filter array
108*4882a593Smuzhiyun */
109*4882a593Smuzhiyun struct pt_filters {
110*4882a593Smuzhiyun struct pt_filter filter[PT_FILTERS_NUM];
111*4882a593Smuzhiyun unsigned int nr_filters;
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /**
115*4882a593Smuzhiyun * struct pt - per-cpu pt context
116*4882a593Smuzhiyun * @handle: perf output handle
117*4882a593Smuzhiyun * @filters: last configured filters
118*4882a593Smuzhiyun * @handle_nmi: do handle PT PMI on this cpu, there's an active event
119*4882a593Smuzhiyun * @vmx_on: 1 if VMX is ON on this cpu
120*4882a593Smuzhiyun * @output_base: cached RTIT_OUTPUT_BASE MSR value
121*4882a593Smuzhiyun * @output_mask: cached RTIT_OUTPUT_MASK MSR value
122*4882a593Smuzhiyun */
123*4882a593Smuzhiyun struct pt {
124*4882a593Smuzhiyun struct perf_output_handle handle;
125*4882a593Smuzhiyun struct pt_filters filters;
126*4882a593Smuzhiyun int handle_nmi;
127*4882a593Smuzhiyun int vmx_on;
128*4882a593Smuzhiyun u64 output_base;
129*4882a593Smuzhiyun u64 output_mask;
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun #endif /* __INTEL_PT_H__ */
133