1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2013 Advanced Micro Devices, Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Steven Kinney <Steven.Kinney@amd.com> 6*4882a593Smuzhiyun * Author: Suravee Suthikulpanit <Suraveee.Suthikulpanit@amd.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _PERF_EVENT_AMD_IOMMU_H_ 10*4882a593Smuzhiyun #define _PERF_EVENT_AMD_IOMMU_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* iommu pc mmio region register indexes */ 13*4882a593Smuzhiyun #define IOMMU_PC_COUNTER_REG 0x00 14*4882a593Smuzhiyun #define IOMMU_PC_COUNTER_SRC_REG 0x08 15*4882a593Smuzhiyun #define IOMMU_PC_PASID_MATCH_REG 0x10 16*4882a593Smuzhiyun #define IOMMU_PC_DOMID_MATCH_REG 0x18 17*4882a593Smuzhiyun #define IOMMU_PC_DEVID_MATCH_REG 0x20 18*4882a593Smuzhiyun #define IOMMU_PC_COUNTER_REPORT_REG 0x28 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* maximun specified bank/counters */ 21*4882a593Smuzhiyun #define PC_MAX_SPEC_BNKS 64 22*4882a593Smuzhiyun #define PC_MAX_SPEC_CNTRS 16 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct amd_iommu; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* amd_iommu_init.c external support functions */ 27*4882a593Smuzhiyun extern int amd_iommu_get_num_iommus(void); 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun extern bool amd_iommu_pc_supported(void); 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun extern u8 amd_iommu_pc_get_max_banks(unsigned int idx); 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun extern u8 amd_iommu_pc_get_max_counters(unsigned int idx); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 36*4882a593Smuzhiyun u8 fxn, u64 *value); 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 39*4882a593Smuzhiyun u8 fxn, u64 *value); 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun extern struct amd_iommu *get_amd_iommu(int idx); 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #endif /*_PERF_EVENT_AMD_IOMMU_H_*/ 44