1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /* -*- linux-c -*- ------------------------------------------------------- *
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 1991, 1992 Linus Torvalds
5*4882a593Smuzhiyun * Copyright 2007 rPath, Inc. - All Rights Reserved
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * ----------------------------------------------------------------------- */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun /*
10*4882a593Smuzhiyun * Prepare the machine for transition to protected mode.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "boot.h"
14*4882a593Smuzhiyun #include <asm/segment.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun * Invoke the realmode switch hook if present; otherwise
18*4882a593Smuzhiyun * disable all interrupts.
19*4882a593Smuzhiyun */
realmode_switch_hook(void)20*4882a593Smuzhiyun static void realmode_switch_hook(void)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun if (boot_params.hdr.realmode_swtch) {
23*4882a593Smuzhiyun asm volatile("lcallw *%0"
24*4882a593Smuzhiyun : : "m" (boot_params.hdr.realmode_swtch)
25*4882a593Smuzhiyun : "eax", "ebx", "ecx", "edx");
26*4882a593Smuzhiyun } else {
27*4882a593Smuzhiyun asm volatile("cli");
28*4882a593Smuzhiyun outb(0x80, 0x70); /* Disable NMI */
29*4882a593Smuzhiyun io_delay();
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun * Disable all interrupts at the legacy PIC.
35*4882a593Smuzhiyun */
mask_all_interrupts(void)36*4882a593Smuzhiyun static void mask_all_interrupts(void)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun outb(0xff, 0xa1); /* Mask all interrupts on the secondary PIC */
39*4882a593Smuzhiyun io_delay();
40*4882a593Smuzhiyun outb(0xfb, 0x21); /* Mask all but cascade on the primary PIC */
41*4882a593Smuzhiyun io_delay();
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /*
45*4882a593Smuzhiyun * Reset IGNNE# if asserted in the FPU.
46*4882a593Smuzhiyun */
reset_coprocessor(void)47*4882a593Smuzhiyun static void reset_coprocessor(void)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun outb(0, 0xf0);
50*4882a593Smuzhiyun io_delay();
51*4882a593Smuzhiyun outb(0, 0xf1);
52*4882a593Smuzhiyun io_delay();
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * Set up the GDT
57*4882a593Smuzhiyun */
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun struct gdt_ptr {
60*4882a593Smuzhiyun u16 len;
61*4882a593Smuzhiyun u32 ptr;
62*4882a593Smuzhiyun } __attribute__((packed));
63*4882a593Smuzhiyun
setup_gdt(void)64*4882a593Smuzhiyun static void setup_gdt(void)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun /* There are machines which are known to not boot with the GDT
67*4882a593Smuzhiyun being 8-byte unaligned. Intel recommends 16 byte alignment. */
68*4882a593Smuzhiyun static const u64 boot_gdt[] __attribute__((aligned(16))) = {
69*4882a593Smuzhiyun /* CS: code, read/execute, 4 GB, base 0 */
70*4882a593Smuzhiyun [GDT_ENTRY_BOOT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff),
71*4882a593Smuzhiyun /* DS: data, read/write, 4 GB, base 0 */
72*4882a593Smuzhiyun [GDT_ENTRY_BOOT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff),
73*4882a593Smuzhiyun /* TSS: 32-bit tss, 104 bytes, base 4096 */
74*4882a593Smuzhiyun /* We only have a TSS here to keep Intel VT happy;
75*4882a593Smuzhiyun we don't actually use it for anything. */
76*4882a593Smuzhiyun [GDT_ENTRY_BOOT_TSS] = GDT_ENTRY(0x0089, 4096, 103),
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun /* Xen HVM incorrectly stores a pointer to the gdt_ptr, instead
79*4882a593Smuzhiyun of the gdt_ptr contents. Thus, make it static so it will
80*4882a593Smuzhiyun stay in memory, at least long enough that we switch to the
81*4882a593Smuzhiyun proper kernel GDT. */
82*4882a593Smuzhiyun static struct gdt_ptr gdt;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun gdt.len = sizeof(boot_gdt)-1;
85*4882a593Smuzhiyun gdt.ptr = (u32)&boot_gdt + (ds() << 4);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun asm volatile("lgdtl %0" : : "m" (gdt));
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /*
91*4882a593Smuzhiyun * Set up the IDT
92*4882a593Smuzhiyun */
setup_idt(void)93*4882a593Smuzhiyun static void setup_idt(void)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun static const struct gdt_ptr null_idt = {0, 0};
96*4882a593Smuzhiyun asm volatile("lidtl %0" : : "m" (null_idt));
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /*
100*4882a593Smuzhiyun * Actual invocation sequence
101*4882a593Smuzhiyun */
go_to_protected_mode(void)102*4882a593Smuzhiyun void go_to_protected_mode(void)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun /* Hook before leaving real mode, also disables interrupts */
105*4882a593Smuzhiyun realmode_switch_hook();
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* Enable the A20 gate */
108*4882a593Smuzhiyun if (enable_a20()) {
109*4882a593Smuzhiyun puts("A20 gate not responding, unable to boot...\n");
110*4882a593Smuzhiyun die();
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* Reset coprocessor (IGNNE#) */
114*4882a593Smuzhiyun reset_coprocessor();
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun /* Mask all interrupts in the PIC */
117*4882a593Smuzhiyun mask_all_interrupts();
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* Actual transition to protected mode... */
120*4882a593Smuzhiyun setup_idt();
121*4882a593Smuzhiyun setup_gdt();
122*4882a593Smuzhiyun protected_mode_jump(boot_params.hdr.code32_start,
123*4882a593Smuzhiyun (u32)&boot_params + (ds() << 4));
124*4882a593Smuzhiyun }
125