1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __UM_CACHE_H 3*4882a593Smuzhiyun #define __UM_CACHE_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT) 7*4882a593Smuzhiyun # define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) 8*4882a593Smuzhiyun #elif defined(CONFIG_UML_X86) /* 64-bit */ 9*4882a593Smuzhiyun # define L1_CACHE_SHIFT 6 /* Should be 7 on Intel */ 10*4882a593Smuzhiyun #else 11*4882a593Smuzhiyun /* XXX: this was taken from x86, now it's completely random. Luckily only 12*4882a593Smuzhiyun * affects SMP padding. */ 13*4882a593Smuzhiyun # define L1_CACHE_SHIFT 5 14*4882a593Smuzhiyun #endif 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #endif 19