1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * tsunami.S: High speed MicroSparc-I mmu/cache operations. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <asm/ptrace.h> 9*4882a593Smuzhiyun#include <asm/asm-offsets.h> 10*4882a593Smuzhiyun#include <asm/psr.h> 11*4882a593Smuzhiyun#include <asm/asi.h> 12*4882a593Smuzhiyun#include <asm/page.h> 13*4882a593Smuzhiyun#include <asm/pgtsrmmu.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun .text 16*4882a593Smuzhiyun .align 4 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun .globl tsunami_flush_cache_all, tsunami_flush_cache_mm 19*4882a593Smuzhiyun .globl tsunami_flush_cache_range, tsunami_flush_cache_page 20*4882a593Smuzhiyun .globl tsunami_flush_page_to_ram, tsunami_flush_page_for_dma 21*4882a593Smuzhiyun .globl tsunami_flush_sig_insns 22*4882a593Smuzhiyun .globl tsunami_flush_tlb_all, tsunami_flush_tlb_mm 23*4882a593Smuzhiyun .globl tsunami_flush_tlb_range, tsunami_flush_tlb_page 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Sliiick... */ 26*4882a593Smuzhiyuntsunami_flush_cache_page: 27*4882a593Smuzhiyuntsunami_flush_cache_range: 28*4882a593Smuzhiyun ld [%o0 + VMA_VM_MM], %o0 29*4882a593Smuzhiyuntsunami_flush_cache_mm: 30*4882a593Smuzhiyun ld [%o0 + AOFF_mm_context], %g2 31*4882a593Smuzhiyun cmp %g2, -1 32*4882a593Smuzhiyun be tsunami_flush_cache_out 33*4882a593Smuzhiyuntsunami_flush_cache_all: 34*4882a593Smuzhiyun WINDOW_FLUSH(%g4, %g5) 35*4882a593Smuzhiyuntsunami_flush_page_for_dma: 36*4882a593Smuzhiyun sta %g0, [%g0] ASI_M_IC_FLCLEAR 37*4882a593Smuzhiyun sta %g0, [%g0] ASI_M_DC_FLCLEAR 38*4882a593Smuzhiyuntsunami_flush_cache_out: 39*4882a593Smuzhiyuntsunami_flush_page_to_ram: 40*4882a593Smuzhiyun retl 41*4882a593Smuzhiyun nop 42*4882a593Smuzhiyun 43*4882a593Smuzhiyuntsunami_flush_sig_insns: 44*4882a593Smuzhiyun flush %o1 45*4882a593Smuzhiyun retl 46*4882a593Smuzhiyun flush %o1 + 4 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* More slick stuff... */ 49*4882a593Smuzhiyuntsunami_flush_tlb_range: 50*4882a593Smuzhiyun ld [%o0 + VMA_VM_MM], %o0 51*4882a593Smuzhiyuntsunami_flush_tlb_mm: 52*4882a593Smuzhiyun ld [%o0 + AOFF_mm_context], %g2 53*4882a593Smuzhiyun cmp %g2, -1 54*4882a593Smuzhiyun be tsunami_flush_tlb_out 55*4882a593Smuzhiyuntsunami_flush_tlb_all: 56*4882a593Smuzhiyun mov 0x400, %o1 57*4882a593Smuzhiyun sta %g0, [%o1] ASI_M_FLUSH_PROBE 58*4882a593Smuzhiyun nop 59*4882a593Smuzhiyun nop 60*4882a593Smuzhiyun nop 61*4882a593Smuzhiyun nop 62*4882a593Smuzhiyun nop 63*4882a593Smuzhiyuntsunami_flush_tlb_out: 64*4882a593Smuzhiyun retl 65*4882a593Smuzhiyun nop 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* This one can be done in a fine grained manner... */ 68*4882a593Smuzhiyuntsunami_flush_tlb_page: 69*4882a593Smuzhiyun ld [%o0 + VMA_VM_MM], %o0 70*4882a593Smuzhiyun mov SRMMU_CTX_REG, %g1 71*4882a593Smuzhiyun ld [%o0 + AOFF_mm_context], %o3 72*4882a593Smuzhiyun andn %o1, (PAGE_SIZE - 1), %o1 73*4882a593Smuzhiyun cmp %o3, -1 74*4882a593Smuzhiyun be tsunami_flush_tlb_page_out 75*4882a593Smuzhiyun lda [%g1] ASI_M_MMUREGS, %g5 76*4882a593Smuzhiyun sta %o3, [%g1] ASI_M_MMUREGS 77*4882a593Smuzhiyun sta %g0, [%o1] ASI_M_FLUSH_PROBE 78*4882a593Smuzhiyun nop 79*4882a593Smuzhiyun nop 80*4882a593Smuzhiyun nop 81*4882a593Smuzhiyun nop 82*4882a593Smuzhiyun nop 83*4882a593Smuzhiyuntsunami_flush_tlb_page_out: 84*4882a593Smuzhiyun retl 85*4882a593Smuzhiyun sta %g5, [%g1] ASI_M_MMUREGS 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun#define MIRROR_BLOCK(dst, src, offset, t0, t1, t2, t3) \ 88*4882a593Smuzhiyun ldd [src + offset + 0x18], t0; \ 89*4882a593Smuzhiyun std t0, [dst + offset + 0x18]; \ 90*4882a593Smuzhiyun ldd [src + offset + 0x10], t2; \ 91*4882a593Smuzhiyun std t2, [dst + offset + 0x10]; \ 92*4882a593Smuzhiyun ldd [src + offset + 0x08], t0; \ 93*4882a593Smuzhiyun std t0, [dst + offset + 0x08]; \ 94*4882a593Smuzhiyun ldd [src + offset + 0x00], t2; \ 95*4882a593Smuzhiyun std t2, [dst + offset + 0x00]; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyuntsunami_copy_1page: 98*4882a593Smuzhiyun/* NOTE: This routine has to be shorter than 70insns --jj */ 99*4882a593Smuzhiyun or %g0, (PAGE_SIZE >> 8), %g1 100*4882a593Smuzhiyun1: 101*4882a593Smuzhiyun MIRROR_BLOCK(%o0, %o1, 0x00, %o2, %o3, %o4, %o5) 102*4882a593Smuzhiyun MIRROR_BLOCK(%o0, %o1, 0x20, %o2, %o3, %o4, %o5) 103*4882a593Smuzhiyun MIRROR_BLOCK(%o0, %o1, 0x40, %o2, %o3, %o4, %o5) 104*4882a593Smuzhiyun MIRROR_BLOCK(%o0, %o1, 0x60, %o2, %o3, %o4, %o5) 105*4882a593Smuzhiyun MIRROR_BLOCK(%o0, %o1, 0x80, %o2, %o3, %o4, %o5) 106*4882a593Smuzhiyun MIRROR_BLOCK(%o0, %o1, 0xa0, %o2, %o3, %o4, %o5) 107*4882a593Smuzhiyun MIRROR_BLOCK(%o0, %o1, 0xc0, %o2, %o3, %o4, %o5) 108*4882a593Smuzhiyun MIRROR_BLOCK(%o0, %o1, 0xe0, %o2, %o3, %o4, %o5) 109*4882a593Smuzhiyun subcc %g1, 1, %g1 110*4882a593Smuzhiyun add %o0, 0x100, %o0 111*4882a593Smuzhiyun bne 1b 112*4882a593Smuzhiyun add %o1, 0x100, %o1 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun .globl tsunami_setup_blockops 115*4882a593Smuzhiyuntsunami_setup_blockops: 116*4882a593Smuzhiyun sethi %hi(__copy_1page), %o0 117*4882a593Smuzhiyun or %o0, %lo(__copy_1page), %o0 118*4882a593Smuzhiyun sethi %hi(tsunami_copy_1page), %o1 119*4882a593Smuzhiyun or %o1, %lo(tsunami_copy_1page), %o1 120*4882a593Smuzhiyun sethi %hi(tsunami_setup_blockops), %o2 121*4882a593Smuzhiyun or %o2, %lo(tsunami_setup_blockops), %o2 122*4882a593Smuzhiyun ld [%o1], %o4 123*4882a593Smuzhiyun1: add %o1, 4, %o1 124*4882a593Smuzhiyun st %o4, [%o0] 125*4882a593Smuzhiyun add %o0, 4, %o0 126*4882a593Smuzhiyun cmp %o1, %o2 127*4882a593Smuzhiyun bne 1b 128*4882a593Smuzhiyun ld [%o1], %o4 129*4882a593Smuzhiyun sta %g0, [%g0] ASI_M_IC_FLCLEAR 130*4882a593Smuzhiyun sta %g0, [%g0] ASI_M_DC_FLCLEAR 131*4882a593Smuzhiyun retl 132*4882a593Smuzhiyun nop 133