1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*4882a593Smuzhiyun #ifndef _SPARC64_PSTATE_H 3*4882a593Smuzhiyun #define _SPARC64_PSTATE_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/const.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* The V9 PSTATE Register (with SpitFire extensions). 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * ----------------------------------------------------------------------- 10*4882a593Smuzhiyun * | Resv | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG | 11*4882a593Smuzhiyun * ----------------------------------------------------------------------- 12*4882a593Smuzhiyun * 63 12 11 10 9 8 7 6 5 4 3 2 1 0 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun /* IG on V9 conflicts with MCDE on M7. PSTATE_MCDE will only be used on 15*4882a593Smuzhiyun * processors that support ADI which do not use IG, hence there is no 16*4882a593Smuzhiyun * functional conflict 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define PSTATE_IG _AC(0x0000000000000800,UL) /* Interrupt Globals. */ 19*4882a593Smuzhiyun #define PSTATE_MCDE _AC(0x0000000000000800,UL) /* MCD Enable */ 20*4882a593Smuzhiyun #define PSTATE_MG _AC(0x0000000000000400,UL) /* MMU Globals. */ 21*4882a593Smuzhiyun #define PSTATE_CLE _AC(0x0000000000000200,UL) /* Current Little Endian.*/ 22*4882a593Smuzhiyun #define PSTATE_TLE _AC(0x0000000000000100,UL) /* Trap Little Endian. */ 23*4882a593Smuzhiyun #define PSTATE_MM _AC(0x00000000000000c0,UL) /* Memory Model. */ 24*4882a593Smuzhiyun #define PSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TotalStoreOrder */ 25*4882a593Smuzhiyun #define PSTATE_PSO _AC(0x0000000000000040,UL) /* MM: PartialStoreOrder */ 26*4882a593Smuzhiyun #define PSTATE_RMO _AC(0x0000000000000080,UL) /* MM: RelaxedMemoryOrder*/ 27*4882a593Smuzhiyun #define PSTATE_RED _AC(0x0000000000000020,UL) /* Reset Error Debug. */ 28*4882a593Smuzhiyun #define PSTATE_PEF _AC(0x0000000000000010,UL) /* Floating Point Enable.*/ 29*4882a593Smuzhiyun #define PSTATE_AM _AC(0x0000000000000008,UL) /* Address Mask. */ 30*4882a593Smuzhiyun #define PSTATE_PRIV _AC(0x0000000000000004,UL) /* Privilege. */ 31*4882a593Smuzhiyun #define PSTATE_IE _AC(0x0000000000000002,UL) /* Interrupt Enable. */ 32*4882a593Smuzhiyun #define PSTATE_AG _AC(0x0000000000000001,UL) /* Alternate Globals. */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* The V9 TSTATE Register (with SpitFire and Linux extensions). 35*4882a593Smuzhiyun * 36*4882a593Smuzhiyun * --------------------------------------------------------------------- 37*4882a593Smuzhiyun * | Resv | GL | CCR | ASI | %pil | PSTATE | Resv | CWP | 38*4882a593Smuzhiyun * --------------------------------------------------------------------- 39*4882a593Smuzhiyun * 63 43 42 40 39 32 31 24 23 20 19 8 7 5 4 0 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun #define TSTATE_GL _AC(0x0000070000000000,UL) /* Global reg level */ 42*4882a593Smuzhiyun #define TSTATE_CCR _AC(0x000000ff00000000,UL) /* Condition Codes. */ 43*4882a593Smuzhiyun #define TSTATE_XCC _AC(0x000000f000000000,UL) /* Condition Codes. */ 44*4882a593Smuzhiyun #define TSTATE_XNEG _AC(0x0000008000000000,UL) /* %xcc Negative. */ 45*4882a593Smuzhiyun #define TSTATE_XZERO _AC(0x0000004000000000,UL) /* %xcc Zero. */ 46*4882a593Smuzhiyun #define TSTATE_XOVFL _AC(0x0000002000000000,UL) /* %xcc Overflow. */ 47*4882a593Smuzhiyun #define TSTATE_XCARRY _AC(0x0000001000000000,UL) /* %xcc Carry. */ 48*4882a593Smuzhiyun #define TSTATE_ICC _AC(0x0000000f00000000,UL) /* Condition Codes. */ 49*4882a593Smuzhiyun #define TSTATE_INEG _AC(0x0000000800000000,UL) /* %icc Negative. */ 50*4882a593Smuzhiyun #define TSTATE_IZERO _AC(0x0000000400000000,UL) /* %icc Zero. */ 51*4882a593Smuzhiyun #define TSTATE_IOVFL _AC(0x0000000200000000,UL) /* %icc Overflow. */ 52*4882a593Smuzhiyun #define TSTATE_ICARRY _AC(0x0000000100000000,UL) /* %icc Carry. */ 53*4882a593Smuzhiyun #define TSTATE_ASI _AC(0x00000000ff000000,UL) /* AddrSpace ID. */ 54*4882a593Smuzhiyun #define TSTATE_PIL _AC(0x0000000000f00000,UL) /* %pil (Linux traps)*/ 55*4882a593Smuzhiyun #define TSTATE_PSTATE _AC(0x00000000000fff00,UL) /* PSTATE. */ 56*4882a593Smuzhiyun /* IG on V9 conflicts with MCDE on M7. TSTATE_MCDE will only be used on 57*4882a593Smuzhiyun * processors that support ADI which do not support IG, hence there is 58*4882a593Smuzhiyun * no functional conflict 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define TSTATE_IG _AC(0x0000000000080000,UL) /* Interrupt Globals.*/ 61*4882a593Smuzhiyun #define TSTATE_MCDE _AC(0x0000000000080000,UL) /* MCD enable. */ 62*4882a593Smuzhiyun #define TSTATE_MG _AC(0x0000000000040000,UL) /* MMU Globals. */ 63*4882a593Smuzhiyun #define TSTATE_CLE _AC(0x0000000000020000,UL) /* CurrLittleEndian. */ 64*4882a593Smuzhiyun #define TSTATE_TLE _AC(0x0000000000010000,UL) /* TrapLittleEndian. */ 65*4882a593Smuzhiyun #define TSTATE_MM _AC(0x000000000000c000,UL) /* Memory Model. */ 66*4882a593Smuzhiyun #define TSTATE_TSO _AC(0x0000000000000000,UL) /* MM: TSO */ 67*4882a593Smuzhiyun #define TSTATE_PSO _AC(0x0000000000004000,UL) /* MM: PSO */ 68*4882a593Smuzhiyun #define TSTATE_RMO _AC(0x0000000000008000,UL) /* MM: RMO */ 69*4882a593Smuzhiyun #define TSTATE_RED _AC(0x0000000000002000,UL) /* Reset Error Debug.*/ 70*4882a593Smuzhiyun #define TSTATE_PEF _AC(0x0000000000001000,UL) /* FPU Enable. */ 71*4882a593Smuzhiyun #define TSTATE_AM _AC(0x0000000000000800,UL) /* Address Mask. */ 72*4882a593Smuzhiyun #define TSTATE_PRIV _AC(0x0000000000000400,UL) /* Privilege. */ 73*4882a593Smuzhiyun #define TSTATE_IE _AC(0x0000000000000200,UL) /* Interrupt Enable. */ 74*4882a593Smuzhiyun #define TSTATE_AG _AC(0x0000000000000100,UL) /* Alternate Globals.*/ 75*4882a593Smuzhiyun #define TSTATE_SYSCALL _AC(0x0000000000000020,UL) /* in syscall trap */ 76*4882a593Smuzhiyun #define TSTATE_CWP _AC(0x000000000000001f,UL) /* Curr Win-Pointer. */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* Floating-Point Registers State Register. 79*4882a593Smuzhiyun * 80*4882a593Smuzhiyun * -------------------------------- 81*4882a593Smuzhiyun * | Resv | FEF | DU | DL | 82*4882a593Smuzhiyun * -------------------------------- 83*4882a593Smuzhiyun * 63 3 2 1 0 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun #define FPRS_FEF _AC(0x0000000000000004,UL) /* FPU Enable. */ 86*4882a593Smuzhiyun #define FPRS_DU _AC(0x0000000000000002,UL) /* Dirty Upper. */ 87*4882a593Smuzhiyun #define FPRS_DL _AC(0x0000000000000001,UL) /* Dirty Lower. */ 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* Version Register. 90*4882a593Smuzhiyun * 91*4882a593Smuzhiyun * ------------------------------------------------------ 92*4882a593Smuzhiyun * | MANUF | IMPL | MASK | Resv | MAXTL | Resv | MAXWIN | 93*4882a593Smuzhiyun * ------------------------------------------------------ 94*4882a593Smuzhiyun * 63 48 47 32 31 24 23 16 15 8 7 5 4 0 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun #define VERS_MANUF _AC(0xffff000000000000,UL) /* Manufacturer. */ 97*4882a593Smuzhiyun #define VERS_IMPL _AC(0x0000ffff00000000,UL) /* Implementation. */ 98*4882a593Smuzhiyun #define VERS_MASK _AC(0x00000000ff000000,UL) /* Mask Set Revision.*/ 99*4882a593Smuzhiyun #define VERS_MAXTL _AC(0x000000000000ff00,UL) /* Max Trap Level. */ 100*4882a593Smuzhiyun #define VERS_MAXWIN _AC(0x000000000000001f,UL) /* Max RegWindow Idx.*/ 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* Compatibility Feature Register (%asr26), SPARC-T4 and later */ 103*4882a593Smuzhiyun #define CFR_AES _AC(0x0000000000000001,UL) /* Supports AES opcodes */ 104*4882a593Smuzhiyun #define CFR_DES _AC(0x0000000000000002,UL) /* Supports DES opcodes */ 105*4882a593Smuzhiyun #define CFR_KASUMI _AC(0x0000000000000004,UL) /* Supports KASUMI opcodes */ 106*4882a593Smuzhiyun #define CFR_CAMELLIA _AC(0x0000000000000008,UL) /* Supports CAMELLIA opcodes*/ 107*4882a593Smuzhiyun #define CFR_MD5 _AC(0x0000000000000010,UL) /* Supports MD5 opcodes */ 108*4882a593Smuzhiyun #define CFR_SHA1 _AC(0x0000000000000020,UL) /* Supports SHA1 opcodes */ 109*4882a593Smuzhiyun #define CFR_SHA256 _AC(0x0000000000000040,UL) /* Supports SHA256 opcodes */ 110*4882a593Smuzhiyun #define CFR_SHA512 _AC(0x0000000000000080,UL) /* Supports SHA512 opcodes */ 111*4882a593Smuzhiyun #define CFR_MPMUL _AC(0x0000000000000100,UL) /* Supports MPMUL opcodes */ 112*4882a593Smuzhiyun #define CFR_MONTMUL _AC(0x0000000000000200,UL) /* Supports MONTMUL opcodes */ 113*4882a593Smuzhiyun #define CFR_MONTSQR _AC(0x0000000000000400,UL) /* Supports MONTSQR opcodes */ 114*4882a593Smuzhiyun #define CFR_CRC32C _AC(0x0000000000000800,UL) /* Supports CRC32C opcodes */ 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #endif /* !(_SPARC64_PSTATE_H) */ 117