1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*4882a593Smuzhiyun /*---------------------------------------- 3*4882a593Smuzhiyun PERFORMANCE INSTRUMENTATION 4*4882a593Smuzhiyun Guillaume Thouvenin 08/10/98 5*4882a593Smuzhiyun David S. Miller 10/06/98 6*4882a593Smuzhiyun ---------------------------------------*/ 7*4882a593Smuzhiyun #ifndef PERF_COUNTER_API 8*4882a593Smuzhiyun #define PERF_COUNTER_API 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* sys_perfctr() interface. First arg is operation code 11*4882a593Smuzhiyun * from enumeration below. The meaning of further arguments 12*4882a593Smuzhiyun * are determined by the operation code. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * NOTE: This system call is no longer provided, use the perf_events 15*4882a593Smuzhiyun * infrastructure. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * Pointers which are passed by the user are pointers to 64-bit 18*4882a593Smuzhiyun * integers. 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * Once enabled, performance counter state is retained until the 21*4882a593Smuzhiyun * process either exits or performs an exec. That is, performance 22*4882a593Smuzhiyun * counters remain enabled for fork/clone children. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun enum perfctr_opcode { 25*4882a593Smuzhiyun /* Enable UltraSparc performance counters, ARG0 is pointer 26*4882a593Smuzhiyun * to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer 27*4882a593Smuzhiyun * to 64-bit accumulator for D1 counter. ARG2 is a pointer to 28*4882a593Smuzhiyun * the initial PCR register value to use. 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun PERFCTR_ON, 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Disable UltraSparc performance counters. The PCR is written 33*4882a593Smuzhiyun * with zero and the user counter accumulator pointers and 34*4882a593Smuzhiyun * working PCR register value are forgotten. 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun PERFCTR_OFF, 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Add current D0 and D1 PIC values into user pointers given 39*4882a593Smuzhiyun * in PERFCTR_ON operation. The PIC is cleared before returning. 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun PERFCTR_READ, 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Clear the PIC register. */ 44*4882a593Smuzhiyun PERFCTR_CLRPIC, 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Begin using a new PCR value, the pointer to which is passed 47*4882a593Smuzhiyun * in ARG0. The PIC is also cleared after the new PCR value is 48*4882a593Smuzhiyun * written. 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun PERFCTR_SETPCR, 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Store in pointer given in ARG0 the current PCR register value 53*4882a593Smuzhiyun * being used. 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun PERFCTR_GETPCR 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define PRIV 0x00000001 59*4882a593Smuzhiyun #define SYS 0x00000002 60*4882a593Smuzhiyun #define USR 0x00000004 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* Pic.S0 Selection Bit Field Encoding, Ultra-I/II */ 63*4882a593Smuzhiyun #define CYCLE_CNT 0x00000000 64*4882a593Smuzhiyun #define INSTR_CNT 0x00000010 65*4882a593Smuzhiyun #define DISPATCH0_IC_MISS 0x00000020 66*4882a593Smuzhiyun #define DISPATCH0_STOREBUF 0x00000030 67*4882a593Smuzhiyun #define IC_REF 0x00000080 68*4882a593Smuzhiyun #define DC_RD 0x00000090 69*4882a593Smuzhiyun #define DC_WR 0x000000A0 70*4882a593Smuzhiyun #define LOAD_USE 0x000000B0 71*4882a593Smuzhiyun #define EC_REF 0x000000C0 72*4882a593Smuzhiyun #define EC_WRITE_HIT_RDO 0x000000D0 73*4882a593Smuzhiyun #define EC_SNOOP_INV 0x000000E0 74*4882a593Smuzhiyun #define EC_RD_HIT 0x000000F0 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* Pic.S0 Selection Bit Field Encoding, Ultra-III */ 77*4882a593Smuzhiyun #define US3_CYCLE_CNT 0x00000000 78*4882a593Smuzhiyun #define US3_INSTR_CNT 0x00000010 79*4882a593Smuzhiyun #define US3_DISPATCH0_IC_MISS 0x00000020 80*4882a593Smuzhiyun #define US3_DISPATCH0_BR_TGT 0x00000030 81*4882a593Smuzhiyun #define US3_DISPATCH0_2ND_BR 0x00000040 82*4882a593Smuzhiyun #define US3_RSTALL_STOREQ 0x00000050 83*4882a593Smuzhiyun #define US3_RSTALL_IU_USE 0x00000060 84*4882a593Smuzhiyun #define US3_IC_REF 0x00000080 85*4882a593Smuzhiyun #define US3_DC_RD 0x00000090 86*4882a593Smuzhiyun #define US3_DC_WR 0x000000a0 87*4882a593Smuzhiyun #define US3_EC_REF 0x000000c0 88*4882a593Smuzhiyun #define US3_EC_WR_HIT_RTO 0x000000d0 89*4882a593Smuzhiyun #define US3_EC_SNOOP_INV 0x000000e0 90*4882a593Smuzhiyun #define US3_EC_RD_MISS 0x000000f0 91*4882a593Smuzhiyun #define US3_PC_PORT0_RD 0x00000100 92*4882a593Smuzhiyun #define US3_SI_SNOOP 0x00000110 93*4882a593Smuzhiyun #define US3_SI_CIQ_FLOW 0x00000120 94*4882a593Smuzhiyun #define US3_SI_OWNED 0x00000130 95*4882a593Smuzhiyun #define US3_SW_COUNT_0 0x00000140 96*4882a593Smuzhiyun #define US3_IU_BR_MISS_TAKEN 0x00000150 97*4882a593Smuzhiyun #define US3_IU_BR_COUNT_TAKEN 0x00000160 98*4882a593Smuzhiyun #define US3_DISP_RS_MISPRED 0x00000170 99*4882a593Smuzhiyun #define US3_FA_PIPE_COMPL 0x00000180 100*4882a593Smuzhiyun #define US3_MC_READS_0 0x00000200 101*4882a593Smuzhiyun #define US3_MC_READS_1 0x00000210 102*4882a593Smuzhiyun #define US3_MC_READS_2 0x00000220 103*4882a593Smuzhiyun #define US3_MC_READS_3 0x00000230 104*4882a593Smuzhiyun #define US3_MC_STALLS_0 0x00000240 105*4882a593Smuzhiyun #define US3_MC_STALLS_2 0x00000250 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* Pic.S1 Selection Bit Field Encoding, Ultra-I/II */ 108*4882a593Smuzhiyun #define CYCLE_CNT_D1 0x00000000 109*4882a593Smuzhiyun #define INSTR_CNT_D1 0x00000800 110*4882a593Smuzhiyun #define DISPATCH0_IC_MISPRED 0x00001000 111*4882a593Smuzhiyun #define DISPATCH0_FP_USE 0x00001800 112*4882a593Smuzhiyun #define IC_HIT 0x00004000 113*4882a593Smuzhiyun #define DC_RD_HIT 0x00004800 114*4882a593Smuzhiyun #define DC_WR_HIT 0x00005000 115*4882a593Smuzhiyun #define LOAD_USE_RAW 0x00005800 116*4882a593Smuzhiyun #define EC_HIT 0x00006000 117*4882a593Smuzhiyun #define EC_WB 0x00006800 118*4882a593Smuzhiyun #define EC_SNOOP_CB 0x00007000 119*4882a593Smuzhiyun #define EC_IT_HIT 0x00007800 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* Pic.S1 Selection Bit Field Encoding, Ultra-III */ 122*4882a593Smuzhiyun #define US3_CYCLE_CNT_D1 0x00000000 123*4882a593Smuzhiyun #define US3_INSTR_CNT_D1 0x00000800 124*4882a593Smuzhiyun #define US3_DISPATCH0_MISPRED 0x00001000 125*4882a593Smuzhiyun #define US3_IC_MISS_CANCELLED 0x00001800 126*4882a593Smuzhiyun #define US3_RE_ENDIAN_MISS 0x00002000 127*4882a593Smuzhiyun #define US3_RE_FPU_BYPASS 0x00002800 128*4882a593Smuzhiyun #define US3_RE_DC_MISS 0x00003000 129*4882a593Smuzhiyun #define US3_RE_EC_MISS 0x00003800 130*4882a593Smuzhiyun #define US3_IC_MISS 0x00004000 131*4882a593Smuzhiyun #define US3_DC_RD_MISS 0x00004800 132*4882a593Smuzhiyun #define US3_DC_WR_MISS 0x00005000 133*4882a593Smuzhiyun #define US3_RSTALL_FP_USE 0x00005800 134*4882a593Smuzhiyun #define US3_EC_MISSES 0x00006000 135*4882a593Smuzhiyun #define US3_EC_WB 0x00006800 136*4882a593Smuzhiyun #define US3_EC_SNOOP_CB 0x00007000 137*4882a593Smuzhiyun #define US3_EC_IC_MISS 0x00007800 138*4882a593Smuzhiyun #define US3_RE_PC_MISS 0x00008000 139*4882a593Smuzhiyun #define US3_ITLB_MISS 0x00008800 140*4882a593Smuzhiyun #define US3_DTLB_MISS 0x00009000 141*4882a593Smuzhiyun #define US3_WC_MISS 0x00009800 142*4882a593Smuzhiyun #define US3_WC_SNOOP_CB 0x0000a000 143*4882a593Smuzhiyun #define US3_WC_SCRUBBED 0x0000a800 144*4882a593Smuzhiyun #define US3_WC_WB_WO_READ 0x0000b000 145*4882a593Smuzhiyun #define US3_PC_SOFT_HIT 0x0000c000 146*4882a593Smuzhiyun #define US3_PC_SNOOP_INV 0x0000c800 147*4882a593Smuzhiyun #define US3_PC_HARD_HIT 0x0000d000 148*4882a593Smuzhiyun #define US3_PC_PORT1_RD 0x0000d800 149*4882a593Smuzhiyun #define US3_SW_COUNT_1 0x0000e000 150*4882a593Smuzhiyun #define US3_IU_STAT_BR_MIS_UNTAKEN 0x0000e800 151*4882a593Smuzhiyun #define US3_IU_STAT_BR_COUNT_UNTAKEN 0x0000f000 152*4882a593Smuzhiyun #define US3_PC_MS_MISSES 0x0000f800 153*4882a593Smuzhiyun #define US3_MC_WRITES_0 0x00010800 154*4882a593Smuzhiyun #define US3_MC_WRITES_1 0x00011000 155*4882a593Smuzhiyun #define US3_MC_WRITES_2 0x00011800 156*4882a593Smuzhiyun #define US3_MC_WRITES_3 0x00012000 157*4882a593Smuzhiyun #define US3_MC_STALLS_1 0x00012800 158*4882a593Smuzhiyun #define US3_MC_STALLS_3 0x00013000 159*4882a593Smuzhiyun #define US3_RE_RAW_MISS 0x00013800 160*4882a593Smuzhiyun #define US3_FM_PIPE_COMPLETION 0x00014000 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun struct vcounter_struct { 163*4882a593Smuzhiyun unsigned long long vcnt0; 164*4882a593Smuzhiyun unsigned long long vcnt1; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun #endif /* !(PERF_COUNTER_API) */ 168