1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * turbosparc.h: Defines specific to the TurboSparc module.
4*4882a593Smuzhiyun * This is SRMMU stuff.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #ifndef _SPARC_TURBOSPARC_H
9*4882a593Smuzhiyun #define _SPARC_TURBOSPARC_H
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <asm/asi.h>
12*4882a593Smuzhiyun #include <asm/pgtsrmmu.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /* Bits in the SRMMU control register for TurboSparc modules.
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * -------------------------------------------------------------------
17*4882a593Smuzhiyun * |impl-vers| RSV| PMC |PE|PC| RSV |BM| RFR |IC|DC|PSO|RSV|ICS|NF|ME|
18*4882a593Smuzhiyun * -------------------------------------------------------------------
19*4882a593Smuzhiyun * 31 24 23-21 20-19 18 17 16-15 14 13-10 9 8 7 6-3 2 1 0
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * This indicates whether the TurboSparc is in boot-mode or not.
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * IC: Instruction Cache -- 0 = off, 1 = on
26*4882a593Smuzhiyun * DC: Data Cache -- 0 = off, 1 = 0n
27*4882a593Smuzhiyun *
28*4882a593Smuzhiyun * These bits enable the on-cpu TurboSparc split I/D caches.
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun * ICS: ICache Snooping -- 0 = disable, 1 = enable snooping of icache
31*4882a593Smuzhiyun * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
32*4882a593Smuzhiyun * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
33*4882a593Smuzhiyun *
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define TURBOSPARC_MMUENABLE 0x00000001
37*4882a593Smuzhiyun #define TURBOSPARC_NOFAULT 0x00000002
38*4882a593Smuzhiyun #define TURBOSPARC_ICSNOOP 0x00000004
39*4882a593Smuzhiyun #define TURBOSPARC_PSO 0x00000080
40*4882a593Smuzhiyun #define TURBOSPARC_DCENABLE 0x00000100 /* Enable data cache */
41*4882a593Smuzhiyun #define TURBOSPARC_ICENABLE 0x00000200 /* Enable instruction cache */
42*4882a593Smuzhiyun #define TURBOSPARC_BMODE 0x00004000
43*4882a593Smuzhiyun #define TURBOSPARC_PARITYODD 0x00020000 /* Parity odd, if enabled */
44*4882a593Smuzhiyun #define TURBOSPARC_PCENABLE 0x00040000 /* Enable parity checking */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Bits in the CPU configuration register for TurboSparc modules.
47*4882a593Smuzhiyun *
48*4882a593Smuzhiyun * -------------------------------------------------------
49*4882a593Smuzhiyun * |IOClk|SNP|AXClk| RAH | WS | RSV |SBC|WT|uS2|SE|SCC|
50*4882a593Smuzhiyun * -------------------------------------------------------
51*4882a593Smuzhiyun * 31 30 29-28 27-26 25-23 22-8 7-6 5 4 3 2-0
52*4882a593Smuzhiyun *
53*4882a593Smuzhiyun */
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define TURBOSPARC_SCENABLE 0x00000008 /* Secondary cache enable */
56*4882a593Smuzhiyun #define TURBOSPARC_uS2 0x00000010 /* Swift compatibility mode */
57*4882a593Smuzhiyun #define TURBOSPARC_WTENABLE 0x00000020 /* Write thru for dcache */
58*4882a593Smuzhiyun #define TURBOSPARC_SNENABLE 0x40000000 /* DVMA snoop enable */
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #ifndef __ASSEMBLY__
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* Bits [13:5] select one of 512 instruction cache tags */
turbosparc_inv_insn_tag(unsigned long addr)63*4882a593Smuzhiyun static inline void turbosparc_inv_insn_tag(unsigned long addr)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
66*4882a593Smuzhiyun : /* no outputs */
67*4882a593Smuzhiyun : "r" (addr), "i" (ASI_M_TXTC_TAG)
68*4882a593Smuzhiyun : "memory");
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* Bits [13:5] select one of 512 data cache tags */
turbosparc_inv_data_tag(unsigned long addr)72*4882a593Smuzhiyun static inline void turbosparc_inv_data_tag(unsigned long addr)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
75*4882a593Smuzhiyun : /* no outputs */
76*4882a593Smuzhiyun : "r" (addr), "i" (ASI_M_DATAC_TAG)
77*4882a593Smuzhiyun : "memory");
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
turbosparc_flush_icache(void)80*4882a593Smuzhiyun static inline void turbosparc_flush_icache(void)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun unsigned long addr;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun for (addr = 0; addr < 0x4000; addr += 0x20)
85*4882a593Smuzhiyun turbosparc_inv_insn_tag(addr);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
turbosparc_flush_dcache(void)88*4882a593Smuzhiyun static inline void turbosparc_flush_dcache(void)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun unsigned long addr;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun for (addr = 0; addr < 0x4000; addr += 0x20)
93*4882a593Smuzhiyun turbosparc_inv_data_tag(addr);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
turbosparc_idflash_clear(void)96*4882a593Smuzhiyun static inline void turbosparc_idflash_clear(void)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun unsigned long addr;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun for (addr = 0; addr < 0x4000; addr += 0x20) {
101*4882a593Smuzhiyun turbosparc_inv_insn_tag(addr);
102*4882a593Smuzhiyun turbosparc_inv_data_tag(addr);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
turbosparc_set_ccreg(unsigned long regval)106*4882a593Smuzhiyun static inline void turbosparc_set_ccreg(unsigned long regval)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun __asm__ __volatile__("sta %0, [%1] %2\n\t"
109*4882a593Smuzhiyun : /* no outputs */
110*4882a593Smuzhiyun : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS)
111*4882a593Smuzhiyun : "memory");
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
turbosparc_get_ccreg(void)114*4882a593Smuzhiyun static inline unsigned long turbosparc_get_ccreg(void)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun unsigned long regval;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun __asm__ __volatile__("lda [%1] %2, %0\n\t"
119*4882a593Smuzhiyun : "=r" (regval)
120*4882a593Smuzhiyun : "r" (0x600), "i" (ASI_M_MMUREGS));
121*4882a593Smuzhiyun return regval;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun #endif /* !__ASSEMBLY__ */
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun #endif /* !(_SPARC_TURBOSPARC_H) */
127