1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * tsunami.h: Module specific definitions for Tsunami V8 Sparcs 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _SPARC_TSUNAMI_H 9*4882a593Smuzhiyun #define _SPARC_TSUNAMI_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <asm/asi.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* The MMU control register on the Tsunami: 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * ----------------------------------------------------------------------- 16*4882a593Smuzhiyun * | implvers |SW|AV|DV|MV| RSV |PC|ITD|ALC| RSV |PE| RC |IE|DE|RSV|NF|ME| 17*4882a593Smuzhiyun * ----------------------------------------------------------------------- 18*4882a593Smuzhiyun * 31 24 23 22 21 20 19-18 17 16 14 13-12 11 10-9 8 7 6-2 1 0 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * SW: Enable Software Table Walks 0=off 1=on 21*4882a593Smuzhiyun * AV: Address View bit 22*4882a593Smuzhiyun * DV: Data View bit 23*4882a593Smuzhiyun * MV: Memory View bit 24*4882a593Smuzhiyun * PC: Parity Control 25*4882a593Smuzhiyun * ITD: ITBR disable 26*4882a593Smuzhiyun * ALC: Alternate Cacheable 27*4882a593Smuzhiyun * PE: Parity Enable 0=off 1=on 28*4882a593Smuzhiyun * RC: Refresh Control 29*4882a593Smuzhiyun * IE: Instruction cache Enable 0=off 1=on 30*4882a593Smuzhiyun * DE: Data cache Enable 0=off 1=on 31*4882a593Smuzhiyun * NF: No Fault, same as all other SRMMUs 32*4882a593Smuzhiyun * ME: MMU Enable, same as all other SRMMUs 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define TSUNAMI_SW 0x00800000 36*4882a593Smuzhiyun #define TSUNAMI_AV 0x00400000 37*4882a593Smuzhiyun #define TSUNAMI_DV 0x00200000 38*4882a593Smuzhiyun #define TSUNAMI_MV 0x00100000 39*4882a593Smuzhiyun #define TSUNAMI_PC 0x00020000 40*4882a593Smuzhiyun #define TSUNAMI_ITD 0x00010000 41*4882a593Smuzhiyun #define TSUNAMI_ALC 0x00008000 42*4882a593Smuzhiyun #define TSUNAMI_PE 0x00001000 43*4882a593Smuzhiyun #define TSUNAMI_RCMASK 0x00000C00 44*4882a593Smuzhiyun #define TSUNAMI_IENAB 0x00000200 45*4882a593Smuzhiyun #define TSUNAMI_DENAB 0x00000100 46*4882a593Smuzhiyun #define TSUNAMI_NF 0x00000002 47*4882a593Smuzhiyun #define TSUNAMI_ME 0x00000001 48*4882a593Smuzhiyun tsunami_flush_icache(void)49*4882a593Smuzhiyunstatic inline void tsunami_flush_icache(void) 50*4882a593Smuzhiyun { 51*4882a593Smuzhiyun __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" 52*4882a593Smuzhiyun : /* no outputs */ 53*4882a593Smuzhiyun : "i" (ASI_M_IC_FLCLEAR) 54*4882a593Smuzhiyun : "memory"); 55*4882a593Smuzhiyun } 56*4882a593Smuzhiyun tsunami_flush_dcache(void)57*4882a593Smuzhiyunstatic inline void tsunami_flush_dcache(void) 58*4882a593Smuzhiyun { 59*4882a593Smuzhiyun __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" 60*4882a593Smuzhiyun : /* no outputs */ 61*4882a593Smuzhiyun : "i" (ASI_M_DC_FLCLEAR) 62*4882a593Smuzhiyun : "memory"); 63*4882a593Smuzhiyun } 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif /* !(_SPARC_TSUNAMI_H) */ 66