1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _SPARC_TLBFLUSH_H 3*4882a593Smuzhiyun #define _SPARC_TLBFLUSH_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <asm/cachetlb_32.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define flush_tlb_all() \ 8*4882a593Smuzhiyun sparc32_cachetlb_ops->tlb_all() 9*4882a593Smuzhiyun #define flush_tlb_mm(mm) \ 10*4882a593Smuzhiyun sparc32_cachetlb_ops->tlb_mm(mm) 11*4882a593Smuzhiyun #define flush_tlb_range(vma, start, end) \ 12*4882a593Smuzhiyun sparc32_cachetlb_ops->tlb_range(vma, start, end) 13*4882a593Smuzhiyun #define flush_tlb_page(vma, addr) \ 14*4882a593Smuzhiyun sparc32_cachetlb_ops->tlb_page(vma, addr) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * This is a kludge, until I know better. --zaitcev XXX 18*4882a593Smuzhiyun */ flush_tlb_kernel_range(unsigned long start,unsigned long end)19*4882a593Smuzhiyunstatic inline void flush_tlb_kernel_range(unsigned long start, 20*4882a593Smuzhiyun unsigned long end) 21*4882a593Smuzhiyun { 22*4882a593Smuzhiyun flush_tlb_all(); 23*4882a593Smuzhiyun } 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #endif /* _SPARC_TLBFLUSH_H */ 26