1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * timer.h: Definitions for the timer chips on the Sparc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _SPARC_TIMER_H 10*4882a593Smuzhiyun #define _SPARC_TIMER_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/clocksource.h> 13*4882a593Smuzhiyun #include <linux/irqreturn.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <asm-generic/percpu.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <asm/cpu_type.h> /* For SUN4M_NCPUS */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define SBUS_CLOCK_RATE 2000000 /* 2MHz */ 20*4882a593Smuzhiyun #define TIMER_VALUE_SHIFT 9 21*4882a593Smuzhiyun #define TIMER_VALUE_MASK 0x3fffff 22*4882a593Smuzhiyun #define TIMER_LIMIT_BIT (1 << 31) /* Bit 31 in Counter-Timer register */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* The counter timer register has the value offset by 9 bits. 25*4882a593Smuzhiyun * From sun4m manual: 26*4882a593Smuzhiyun * When a counter reaches the value in the corresponding limit register, 27*4882a593Smuzhiyun * the Limit bit is set and the counter is set to 500 nS (i.e. 0x00000200). 28*4882a593Smuzhiyun * 29*4882a593Smuzhiyun * To compensate for this add one to the value. 30*4882a593Smuzhiyun */ timer_value(unsigned int value)31*4882a593Smuzhiyunstatic inline unsigned int timer_value(unsigned int value) 32*4882a593Smuzhiyun { 33*4882a593Smuzhiyun return (value + 1) << TIMER_VALUE_SHIFT; 34*4882a593Smuzhiyun } 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun extern volatile u32 __iomem *master_l10_counter; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun irqreturn_t notrace timer_interrupt(int dummy, void *dev_id); 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #ifdef CONFIG_SMP 41*4882a593Smuzhiyun DECLARE_PER_CPU(struct clock_event_device, sparc32_clockevent); 42*4882a593Smuzhiyun void register_percpu_ce(int cpu); 43*4882a593Smuzhiyun #endif 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #endif /* !(_SPARC_TIMER_H) */ 46