1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * include/asm/sunbpp.h 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _ASM_SPARC_SUNBPP_H 7*4882a593Smuzhiyun #define _ASM_SPARC_SUNBPP_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun struct bpp_regs { 10*4882a593Smuzhiyun /* DMA registers */ 11*4882a593Smuzhiyun __volatile__ __u32 p_csr; /* DMA Control/Status Register */ 12*4882a593Smuzhiyun __volatile__ __u32 p_addr; /* Address Register */ 13*4882a593Smuzhiyun __volatile__ __u32 p_bcnt; /* Byte Count Register */ 14*4882a593Smuzhiyun __volatile__ __u32 p_tst_csr; /* Test Control/Status (DMA2 only) */ 15*4882a593Smuzhiyun /* Parallel Port registers */ 16*4882a593Smuzhiyun __volatile__ __u16 p_hcr; /* Hardware Configuration Register */ 17*4882a593Smuzhiyun __volatile__ __u16 p_ocr; /* Operation Configuration Register */ 18*4882a593Smuzhiyun __volatile__ __u8 p_dr; /* Parallel Data Register */ 19*4882a593Smuzhiyun __volatile__ __u8 p_tcr; /* Transfer Control Register */ 20*4882a593Smuzhiyun __volatile__ __u8 p_or; /* Output Register */ 21*4882a593Smuzhiyun __volatile__ __u8 p_ir; /* Input Register */ 22*4882a593Smuzhiyun __volatile__ __u16 p_icr; /* Interrupt Control Register */ 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* P_HCR. Time is in increments of SBus clock. */ 26*4882a593Smuzhiyun #define P_HCR_TEST 0x8000 /* Allows buried counters to be read */ 27*4882a593Smuzhiyun #define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */ 28*4882a593Smuzhiyun #define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* P_OCR. */ 31*4882a593Smuzhiyun #define P_OCR_MEM_CLR 0x8000 32*4882a593Smuzhiyun #define P_OCR_DATA_SRC 0x4000 /* ) */ 33*4882a593Smuzhiyun #define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */ 34*4882a593Smuzhiyun #define P_OCR_BUSY_DSEL 0x1000 /* ) selects */ 35*4882a593Smuzhiyun #define P_OCR_ACK_DSEL 0x0800 /* ) */ 36*4882a593Smuzhiyun #define P_OCR_EN_DIAG 0x0400 37*4882a593Smuzhiyun #define P_OCR_BUSY_OP 0x0200 /* Busy operation */ 38*4882a593Smuzhiyun #define P_OCR_ACK_OP 0x0100 /* Ack operation */ 39*4882a593Smuzhiyun #define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */ 40*4882a593Smuzhiyun #define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */ 41*4882a593Smuzhiyun #define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */ 42*4882a593Smuzhiyun #define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* P_TCR */ 45*4882a593Smuzhiyun #define P_TCR_DIR 0x08 46*4882a593Smuzhiyun #define P_TCR_BUSY 0x04 47*4882a593Smuzhiyun #define P_TCR_ACK 0x02 48*4882a593Smuzhiyun #define P_TCR_DS 0x01 /* Strobe */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* P_OR */ 51*4882a593Smuzhiyun #define P_OR_V3 0x20 /* ) */ 52*4882a593Smuzhiyun #define P_OR_V2 0x10 /* ) on Zebra only */ 53*4882a593Smuzhiyun #define P_OR_V1 0x08 /* ) */ 54*4882a593Smuzhiyun #define P_OR_INIT 0x04 55*4882a593Smuzhiyun #define P_OR_AFXN 0x02 /* Auto Feed */ 56*4882a593Smuzhiyun #define P_OR_SLCT_IN 0x01 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* P_IR */ 59*4882a593Smuzhiyun #define P_IR_PE 0x04 60*4882a593Smuzhiyun #define P_IR_SLCT 0x02 61*4882a593Smuzhiyun #define P_IR_ERR 0x01 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* P_ICR */ 64*4882a593Smuzhiyun #define P_DS_IRQ 0x8000 /* RW1 */ 65*4882a593Smuzhiyun #define P_ACK_IRQ 0x4000 /* RW1 */ 66*4882a593Smuzhiyun #define P_BUSY_IRQ 0x2000 /* RW1 */ 67*4882a593Smuzhiyun #define P_PE_IRQ 0x1000 /* RW1 */ 68*4882a593Smuzhiyun #define P_SLCT_IRQ 0x0800 /* RW1 */ 69*4882a593Smuzhiyun #define P_ERR_IRQ 0x0400 /* RW1 */ 70*4882a593Smuzhiyun #define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */ 71*4882a593Smuzhiyun #define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */ 72*4882a593Smuzhiyun #define P_BUSY_IRP 0x0080 /* RW 1= rising edge */ 73*4882a593Smuzhiyun #define P_BUSY_IRQ_EN 0x0040 /* RW */ 74*4882a593Smuzhiyun #define P_PE_IRP 0x0020 /* RW 1= rising edge */ 75*4882a593Smuzhiyun #define P_PE_IRQ_EN 0x0010 /* RW */ 76*4882a593Smuzhiyun #define P_SLCT_IRP 0x0008 /* RW 1= rising edge */ 77*4882a593Smuzhiyun #define P_SLCT_IRQ_EN 0x0004 /* RW */ 78*4882a593Smuzhiyun #define P_ERR_IRP 0x0002 /* RW1 1= rising edge */ 79*4882a593Smuzhiyun #define P_ERR_IRQ_EN 0x0001 /* RW */ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #endif /* !(_ASM_SPARC_SUNBPP_H) */ 82