xref: /OK3568_Linux_fs/kernel/arch/sparc/include/asm/leon_amba.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun *Copyright (C) 2004 Konrad Eisele (eiselekd@web.de,konrad@gaisler.com), Gaisler Research
4*4882a593Smuzhiyun *Copyright (C) 2004 Stefan Holst (mail@s-holst.de), Uni-Stuttgart
5*4882a593Smuzhiyun *Copyright (C) 2009 Daniel Hellstrom (daniel@gaisler.com),Konrad Eisele (konrad@gaisler.com) Aeroflex Gaisler AB
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef LEON_AMBA_H_INCLUDE
9*4882a593Smuzhiyun #define LEON_AMBA_H_INCLUDE
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #ifndef __ASSEMBLY__
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun struct amba_prom_registers {
14*4882a593Smuzhiyun 	unsigned int phys_addr;	/* The physical address of this register */
15*4882a593Smuzhiyun 	unsigned int reg_size;	/* How many bytes does this register take up? */
16*4882a593Smuzhiyun };
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #endif
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun  *  The following defines the bits in the LEON UART Status Registers.
22*4882a593Smuzhiyun  */
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define LEON_REG_UART_STATUS_DR   0x00000001	/* Data Ready */
25*4882a593Smuzhiyun #define LEON_REG_UART_STATUS_TSE  0x00000002	/* TX Send Register Empty */
26*4882a593Smuzhiyun #define LEON_REG_UART_STATUS_THE  0x00000004	/* TX Hold Register Empty */
27*4882a593Smuzhiyun #define LEON_REG_UART_STATUS_BR   0x00000008	/* Break Error */
28*4882a593Smuzhiyun #define LEON_REG_UART_STATUS_OE   0x00000010	/* RX Overrun Error */
29*4882a593Smuzhiyun #define LEON_REG_UART_STATUS_PE   0x00000020	/* RX Parity Error */
30*4882a593Smuzhiyun #define LEON_REG_UART_STATUS_FE   0x00000040	/* RX Framing Error */
31*4882a593Smuzhiyun #define LEON_REG_UART_STATUS_ERR  0x00000078	/* Error Mask */
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun  *  The following defines the bits in the LEON UART Ctrl Registers.
35*4882a593Smuzhiyun  */
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define LEON_REG_UART_CTRL_RE     0x00000001	/* Receiver enable */
38*4882a593Smuzhiyun #define LEON_REG_UART_CTRL_TE     0x00000002	/* Transmitter enable */
39*4882a593Smuzhiyun #define LEON_REG_UART_CTRL_RI     0x00000004	/* Receiver interrupt enable */
40*4882a593Smuzhiyun #define LEON_REG_UART_CTRL_TI     0x00000008	/* Transmitter irq */
41*4882a593Smuzhiyun #define LEON_REG_UART_CTRL_PS     0x00000010	/* Parity select */
42*4882a593Smuzhiyun #define LEON_REG_UART_CTRL_PE     0x00000020	/* Parity enable */
43*4882a593Smuzhiyun #define LEON_REG_UART_CTRL_FL     0x00000040	/* Flow control enable */
44*4882a593Smuzhiyun #define LEON_REG_UART_CTRL_LB     0x00000080	/* Loop Back enable */
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define LEON3_GPTIMER_EN 1
47*4882a593Smuzhiyun #define LEON3_GPTIMER_RL 2
48*4882a593Smuzhiyun #define LEON3_GPTIMER_LD 4
49*4882a593Smuzhiyun #define LEON3_GPTIMER_IRQEN 8
50*4882a593Smuzhiyun #define LEON3_GPTIMER_SEPIRQ 8
51*4882a593Smuzhiyun #define LEON3_GPTIMER_TIMERS 0x7
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #define LEON23_REG_TIMER_CONTROL_EN    0x00000001 /* 1 = enable counting */
54*4882a593Smuzhiyun /* 0 = hold scalar and counter */
55*4882a593Smuzhiyun #define LEON23_REG_TIMER_CONTROL_RL    0x00000002 /* 1 = reload at 0 */
56*4882a593Smuzhiyun 						  /* 0 = stop at 0 */
57*4882a593Smuzhiyun #define LEON23_REG_TIMER_CONTROL_LD    0x00000004 /* 1 = load counter */
58*4882a593Smuzhiyun 						  /* 0 = no function */
59*4882a593Smuzhiyun #define LEON23_REG_TIMER_CONTROL_IQ    0x00000008 /* 1 = irq enable */
60*4882a593Smuzhiyun 						  /* 0 = no function */
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun /*
63*4882a593Smuzhiyun  *  The following defines the bits in the LEON PS/2 Status Registers.
64*4882a593Smuzhiyun  */
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #define LEON_REG_PS2_STATUS_DR   0x00000001	/* Data Ready */
67*4882a593Smuzhiyun #define LEON_REG_PS2_STATUS_PE   0x00000002	/* Parity error */
68*4882a593Smuzhiyun #define LEON_REG_PS2_STATUS_FE   0x00000004	/* Framing error */
69*4882a593Smuzhiyun #define LEON_REG_PS2_STATUS_KI   0x00000008	/* Keyboard inhibit */
70*4882a593Smuzhiyun #define LEON_REG_PS2_STATUS_RF   0x00000010	/* RX buffer full */
71*4882a593Smuzhiyun #define LEON_REG_PS2_STATUS_TF   0x00000020	/* TX buffer full */
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun /*
74*4882a593Smuzhiyun  *  The following defines the bits in the LEON PS/2 Ctrl Registers.
75*4882a593Smuzhiyun  */
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun #define LEON_REG_PS2_CTRL_RE 0x00000001	/* Receiver enable */
78*4882a593Smuzhiyun #define LEON_REG_PS2_CTRL_TE 0x00000002	/* Transmitter enable */
79*4882a593Smuzhiyun #define LEON_REG_PS2_CTRL_RI 0x00000004	/* Keyboard receive irq  */
80*4882a593Smuzhiyun #define LEON_REG_PS2_CTRL_TI 0x00000008	/* Keyboard transmit irq */
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun #define LEON3_IRQMPSTATUS_CPUNR     28
83*4882a593Smuzhiyun #define LEON3_IRQMPSTATUS_BROADCAST 27
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun #define GPTIMER_CONFIG_IRQNT(a)          (((a) >> 3) & 0x1f)
86*4882a593Smuzhiyun #define GPTIMER_CONFIG_ISSEP(a)          ((a) & (1 << 8))
87*4882a593Smuzhiyun #define GPTIMER_CONFIG_NTIMERS(a)        ((a) & (0x7))
88*4882a593Smuzhiyun #define LEON3_GPTIMER_CTRL_PENDING       0x10
89*4882a593Smuzhiyun #define LEON3_GPTIMER_CONFIG_NRTIMERS(c) ((c)->config & 0x7)
90*4882a593Smuzhiyun #define LEON3_GPTIMER_CTRL_ISPENDING(r)  (((r)&LEON3_GPTIMER_CTRL_PENDING) ? 1 : 0)
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #ifndef __ASSEMBLY__
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun struct leon3_irqctrl_regs_map {
95*4882a593Smuzhiyun 	u32 ilevel;
96*4882a593Smuzhiyun 	u32 ipend;
97*4882a593Smuzhiyun 	u32 iforce;
98*4882a593Smuzhiyun 	u32 iclear;
99*4882a593Smuzhiyun 	u32 mpstatus;
100*4882a593Smuzhiyun 	u32 mpbroadcast;
101*4882a593Smuzhiyun 	u32 notused02;
102*4882a593Smuzhiyun 	u32 notused03;
103*4882a593Smuzhiyun 	u32 ampctrl;
104*4882a593Smuzhiyun 	u32 icsel[2];
105*4882a593Smuzhiyun 	u32 notused13;
106*4882a593Smuzhiyun 	u32 notused20;
107*4882a593Smuzhiyun 	u32 notused21;
108*4882a593Smuzhiyun 	u32 notused22;
109*4882a593Smuzhiyun 	u32 notused23;
110*4882a593Smuzhiyun 	u32 mask[16];
111*4882a593Smuzhiyun 	u32 force[16];
112*4882a593Smuzhiyun 	/* Extended IRQ registers */
113*4882a593Smuzhiyun 	u32 intid[16];	/* 0xc0 */
114*4882a593Smuzhiyun 	u32 unused[(0x1000-0x100)/4];
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun struct leon3_apbuart_regs_map {
118*4882a593Smuzhiyun 	u32 data;
119*4882a593Smuzhiyun 	u32 status;
120*4882a593Smuzhiyun 	u32 ctrl;
121*4882a593Smuzhiyun 	u32 scaler;
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun struct leon3_gptimerelem_regs_map {
125*4882a593Smuzhiyun 	u32 val;
126*4882a593Smuzhiyun 	u32 rld;
127*4882a593Smuzhiyun 	u32 ctrl;
128*4882a593Smuzhiyun 	u32 unused;
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun struct leon3_gptimer_regs_map {
132*4882a593Smuzhiyun 	u32 scalar;
133*4882a593Smuzhiyun 	u32 scalar_reload;
134*4882a593Smuzhiyun 	u32 config;
135*4882a593Smuzhiyun 	u32 unused;
136*4882a593Smuzhiyun 	struct leon3_gptimerelem_regs_map e[8];
137*4882a593Smuzhiyun };
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun /*
140*4882a593Smuzhiyun  *  Types and structure used for AMBA Plug & Play bus scanning
141*4882a593Smuzhiyun  */
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun #define AMBA_MAXAPB_DEVS 64
144*4882a593Smuzhiyun #define AMBA_MAXAPB_DEVS_PERBUS 16
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun struct amba_device_table {
147*4882a593Smuzhiyun 	int devnr;		   /* number of devices on AHB or APB bus */
148*4882a593Smuzhiyun 	unsigned int *addr[16];    /* addresses to the devices configuration tables */
149*4882a593Smuzhiyun 	unsigned int allocbits[1]; /* 0=unallocated, 1=allocated driver */
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun struct amba_apbslv_device_table {
153*4882a593Smuzhiyun 	int devnr;		                  /* number of devices on AHB or APB bus */
154*4882a593Smuzhiyun 	unsigned int *addr[AMBA_MAXAPB_DEVS];     /* addresses to the devices configuration tables */
155*4882a593Smuzhiyun 	unsigned int apbmst[AMBA_MAXAPB_DEVS];    /* apb master if a entry is a apb slave */
156*4882a593Smuzhiyun 	unsigned int apbmstidx[AMBA_MAXAPB_DEVS]; /* apb master idx if a entry is a apb slave */
157*4882a593Smuzhiyun 	unsigned int allocbits[4];                /* 0=unallocated, 1=allocated driver */
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun struct amba_confarea_type {
161*4882a593Smuzhiyun 	struct amba_confarea_type *next;/* next bus in chain */
162*4882a593Smuzhiyun 	struct amba_device_table ahbmst;
163*4882a593Smuzhiyun 	struct amba_device_table ahbslv;
164*4882a593Smuzhiyun 	struct amba_apbslv_device_table apbslv;
165*4882a593Smuzhiyun 	unsigned int apbmst;
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun /* collect apb slaves */
169*4882a593Smuzhiyun struct amba_apb_device {
170*4882a593Smuzhiyun 	unsigned int start, irq, bus_id;
171*4882a593Smuzhiyun 	struct amba_confarea_type *bus;
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun /* collect ahb slaves */
175*4882a593Smuzhiyun struct amba_ahb_device {
176*4882a593Smuzhiyun 	unsigned int start[4], irq, bus_id;
177*4882a593Smuzhiyun 	struct amba_confarea_type *bus;
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun struct device_node;
181*4882a593Smuzhiyun void _amba_init(struct device_node *dp, struct device_node ***nextp);
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun extern unsigned long amba_system_id;
184*4882a593Smuzhiyun extern struct leon3_irqctrl_regs_map *leon3_irqctrl_regs;
185*4882a593Smuzhiyun extern struct leon3_gptimer_regs_map *leon3_gptimer_regs;
186*4882a593Smuzhiyun extern struct amba_apb_device leon_percpu_timer_dev[16];
187*4882a593Smuzhiyun extern int leondebug_irq_disable;
188*4882a593Smuzhiyun extern int leon_debug_irqout;
189*4882a593Smuzhiyun extern unsigned long leon3_gptimer_irq;
190*4882a593Smuzhiyun extern unsigned int sparc_leon_eirq;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun #define LEON3_IO_AREA 0xfff00000
195*4882a593Smuzhiyun #define LEON3_CONF_AREA 0xff000
196*4882a593Smuzhiyun #define LEON3_AHB_SLAVE_CONF_AREA (1 << 11)
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun #define LEON3_AHB_CONF_WORDS 8
199*4882a593Smuzhiyun #define LEON3_APB_CONF_WORDS 2
200*4882a593Smuzhiyun #define LEON3_AHB_MASTERS 16
201*4882a593Smuzhiyun #define LEON3_AHB_SLAVES 16
202*4882a593Smuzhiyun #define LEON3_APB_SLAVES 16
203*4882a593Smuzhiyun #define LEON3_APBUARTS 8
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun /* Vendor codes */
206*4882a593Smuzhiyun #define VENDOR_GAISLER   1
207*4882a593Smuzhiyun #define VENDOR_PENDER    2
208*4882a593Smuzhiyun #define VENDOR_ESA       4
209*4882a593Smuzhiyun #define VENDOR_OPENCORES 8
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun /* Gaisler Research device id's */
212*4882a593Smuzhiyun #define GAISLER_LEON3    0x003
213*4882a593Smuzhiyun #define GAISLER_LEON3DSU 0x004
214*4882a593Smuzhiyun #define GAISLER_ETHAHB   0x005
215*4882a593Smuzhiyun #define GAISLER_APBMST   0x006
216*4882a593Smuzhiyun #define GAISLER_AHBUART  0x007
217*4882a593Smuzhiyun #define GAISLER_SRCTRL   0x008
218*4882a593Smuzhiyun #define GAISLER_SDCTRL   0x009
219*4882a593Smuzhiyun #define GAISLER_APBUART  0x00C
220*4882a593Smuzhiyun #define GAISLER_IRQMP    0x00D
221*4882a593Smuzhiyun #define GAISLER_AHBRAM   0x00E
222*4882a593Smuzhiyun #define GAISLER_GPTIMER  0x011
223*4882a593Smuzhiyun #define GAISLER_PCITRG   0x012
224*4882a593Smuzhiyun #define GAISLER_PCISBRG  0x013
225*4882a593Smuzhiyun #define GAISLER_PCIFBRG  0x014
226*4882a593Smuzhiyun #define GAISLER_PCITRACE 0x015
227*4882a593Smuzhiyun #define GAISLER_PCIDMA   0x016
228*4882a593Smuzhiyun #define GAISLER_AHBTRACE 0x017
229*4882a593Smuzhiyun #define GAISLER_ETHDSU   0x018
230*4882a593Smuzhiyun #define GAISLER_PIOPORT  0x01A
231*4882a593Smuzhiyun #define GAISLER_GRGPIO   0x01A
232*4882a593Smuzhiyun #define GAISLER_AHBJTAG  0x01c
233*4882a593Smuzhiyun #define GAISLER_ETHMAC   0x01D
234*4882a593Smuzhiyun #define GAISLER_AHB2AHB  0x020
235*4882a593Smuzhiyun #define GAISLER_USBDC    0x021
236*4882a593Smuzhiyun #define GAISLER_ATACTRL  0x024
237*4882a593Smuzhiyun #define GAISLER_DDRSPA   0x025
238*4882a593Smuzhiyun #define GAISLER_USBEHC   0x026
239*4882a593Smuzhiyun #define GAISLER_USBUHC   0x027
240*4882a593Smuzhiyun #define GAISLER_I2CMST   0x028
241*4882a593Smuzhiyun #define GAISLER_SPICTRL  0x02D
242*4882a593Smuzhiyun #define GAISLER_DDR2SPA  0x02E
243*4882a593Smuzhiyun #define GAISLER_SPIMCTRL 0x045
244*4882a593Smuzhiyun #define GAISLER_LEON4    0x048
245*4882a593Smuzhiyun #define GAISLER_LEON4DSU 0x049
246*4882a593Smuzhiyun #define GAISLER_AHBSTAT  0x052
247*4882a593Smuzhiyun #define GAISLER_FTMCTRL  0x054
248*4882a593Smuzhiyun #define GAISLER_KBD      0x060
249*4882a593Smuzhiyun #define GAISLER_VGA      0x061
250*4882a593Smuzhiyun #define GAISLER_SVGA     0x063
251*4882a593Smuzhiyun #define GAISLER_GRSYSMON 0x066
252*4882a593Smuzhiyun #define GAISLER_GRACECTRL 0x067
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun #define GAISLER_L2TIME   0xffd	/* internal device: leon2 timer */
255*4882a593Smuzhiyun #define GAISLER_L2C      0xffe	/* internal device: leon2compat */
256*4882a593Smuzhiyun #define GAISLER_PLUGPLAY 0xfff	/* internal device: plug & play configarea */
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun /* Chip IDs */
259*4882a593Smuzhiyun #define AEROFLEX_UT699    0x0699
260*4882a593Smuzhiyun #define LEON4_NEXTREME1   0x0102
261*4882a593Smuzhiyun #define GAISLER_GR712RC   0x0712
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun #define amba_vendor(x) (((x) >> 24) & 0xff)
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun #define amba_device(x) (((x) >> 12) & 0xfff)
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun #endif
268