1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* iommu.h: Definitions for the sun5 IOMMU. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 1996, 1999, 2007 David S. Miller (davem@davemloft.net) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _SPARC64_IOMMU_H 7*4882a593Smuzhiyun #define _SPARC64_IOMMU_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* The format of an iopte in the page tables. */ 10*4882a593Smuzhiyun #define IOPTE_VALID 0x8000000000000000UL 11*4882a593Smuzhiyun #define IOPTE_64K 0x2000000000000000UL 12*4882a593Smuzhiyun #define IOPTE_STBUF 0x1000000000000000UL 13*4882a593Smuzhiyun #define IOPTE_INTRA 0x0800000000000000UL 14*4882a593Smuzhiyun #define IOPTE_CONTEXT 0x07ff800000000000UL 15*4882a593Smuzhiyun #define IOPTE_PAGE 0x00007fffffffe000UL 16*4882a593Smuzhiyun #define IOPTE_CACHE 0x0000000000000010UL 17*4882a593Smuzhiyun #define IOPTE_WRITE 0x0000000000000002UL 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define IOMMU_NUM_CTXS 4096 20*4882a593Smuzhiyun #include <asm/iommu-common.h> 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct iommu_arena { 23*4882a593Smuzhiyun unsigned long *map; 24*4882a593Smuzhiyun unsigned int hint; 25*4882a593Smuzhiyun unsigned int limit; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define ATU_64_SPACE_SIZE 0x800000000 /* 32G */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* Data structures for SPARC ATU architecture */ 31*4882a593Smuzhiyun struct atu_iotsb { 32*4882a593Smuzhiyun void *table; /* IOTSB table base virtual addr*/ 33*4882a593Smuzhiyun u64 ra; /* IOTSB table real addr */ 34*4882a593Smuzhiyun u64 dvma_size; /* ranges[3].size or OS slected 32G size */ 35*4882a593Smuzhiyun u64 dvma_base; /* ranges[3].base */ 36*4882a593Smuzhiyun u64 table_size; /* IOTSB table size */ 37*4882a593Smuzhiyun u64 page_size; /* IO PAGE size for IOTSB */ 38*4882a593Smuzhiyun u32 iotsb_num; /* tsbnum is same as iotsb_handle */ 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct atu_ranges { 42*4882a593Smuzhiyun u64 base; 43*4882a593Smuzhiyun u64 size; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct atu { 47*4882a593Smuzhiyun struct atu_ranges *ranges; 48*4882a593Smuzhiyun struct atu_iotsb *iotsb; 49*4882a593Smuzhiyun struct iommu_map_table tbl; 50*4882a593Smuzhiyun u64 base; 51*4882a593Smuzhiyun u64 size; 52*4882a593Smuzhiyun u64 dma_addr_mask; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun struct iommu { 56*4882a593Smuzhiyun struct iommu_map_table tbl; 57*4882a593Smuzhiyun struct atu *atu; 58*4882a593Smuzhiyun spinlock_t lock; 59*4882a593Smuzhiyun u32 dma_addr_mask; 60*4882a593Smuzhiyun iopte_t *page_table; 61*4882a593Smuzhiyun unsigned long iommu_control; 62*4882a593Smuzhiyun unsigned long iommu_tsbbase; 63*4882a593Smuzhiyun unsigned long iommu_flush; 64*4882a593Smuzhiyun unsigned long iommu_flushinv; 65*4882a593Smuzhiyun unsigned long iommu_tags; 66*4882a593Smuzhiyun unsigned long iommu_ctxflush; 67*4882a593Smuzhiyun unsigned long write_complete_reg; 68*4882a593Smuzhiyun unsigned long dummy_page; 69*4882a593Smuzhiyun unsigned long dummy_page_pa; 70*4882a593Smuzhiyun unsigned long ctx_lowest_free; 71*4882a593Smuzhiyun DECLARE_BITMAP(ctx_bitmap, IOMMU_NUM_CTXS); 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun struct strbuf { 75*4882a593Smuzhiyun int strbuf_enabled; 76*4882a593Smuzhiyun unsigned long strbuf_control; 77*4882a593Smuzhiyun unsigned long strbuf_pflush; 78*4882a593Smuzhiyun unsigned long strbuf_fsync; 79*4882a593Smuzhiyun unsigned long strbuf_err_stat; 80*4882a593Smuzhiyun unsigned long strbuf_tag_diag; 81*4882a593Smuzhiyun unsigned long strbuf_line_diag; 82*4882a593Smuzhiyun unsigned long strbuf_ctxflush; 83*4882a593Smuzhiyun unsigned long strbuf_ctxmatch_base; 84*4882a593Smuzhiyun unsigned long strbuf_flushflag_pa; 85*4882a593Smuzhiyun volatile unsigned long *strbuf_flushflag; 86*4882a593Smuzhiyun volatile unsigned long __flushflag_buf[(64+(64-1)) / sizeof(long)]; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun int iommu_table_init(struct iommu *iommu, int tsbsize, 90*4882a593Smuzhiyun u32 dma_offset, u32 dma_addr_mask, 91*4882a593Smuzhiyun int numa_node); 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif /* !(_SPARC64_IOMMU_H) */ 94