1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _LINUX_IOMMU_COMMON_H 3*4882a593Smuzhiyun #define _LINUX_IOMMU_COMMON_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/spinlock_types.h> 6*4882a593Smuzhiyun #include <linux/device.h> 7*4882a593Smuzhiyun #include <asm/page.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define IOMMU_POOL_HASHBITS 4 10*4882a593Smuzhiyun #define IOMMU_NR_POOLS (1 << IOMMU_POOL_HASHBITS) 11*4882a593Smuzhiyun #define IOMMU_ERROR_CODE (~(unsigned long) 0) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct iommu_pool { 14*4882a593Smuzhiyun unsigned long start; 15*4882a593Smuzhiyun unsigned long end; 16*4882a593Smuzhiyun unsigned long hint; 17*4882a593Smuzhiyun spinlock_t lock; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct iommu_map_table { 21*4882a593Smuzhiyun unsigned long table_map_base; 22*4882a593Smuzhiyun unsigned long table_shift; 23*4882a593Smuzhiyun unsigned long nr_pools; 24*4882a593Smuzhiyun void (*lazy_flush)(struct iommu_map_table *); 25*4882a593Smuzhiyun unsigned long poolsize; 26*4882a593Smuzhiyun struct iommu_pool pools[IOMMU_NR_POOLS]; 27*4882a593Smuzhiyun u32 flags; 28*4882a593Smuzhiyun #define IOMMU_HAS_LARGE_POOL 0x00000001 29*4882a593Smuzhiyun #define IOMMU_NO_SPAN_BOUND 0x00000002 30*4882a593Smuzhiyun #define IOMMU_NEED_FLUSH 0x00000004 31*4882a593Smuzhiyun struct iommu_pool large_pool; 32*4882a593Smuzhiyun unsigned long *map; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun extern void iommu_tbl_pool_init(struct iommu_map_table *iommu, 36*4882a593Smuzhiyun unsigned long num_entries, 37*4882a593Smuzhiyun u32 table_shift, 38*4882a593Smuzhiyun void (*lazy_flush)(struct iommu_map_table *), 39*4882a593Smuzhiyun bool large_pool, u32 npools, 40*4882a593Smuzhiyun bool skip_span_boundary_check); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun extern unsigned long iommu_tbl_range_alloc(struct device *dev, 43*4882a593Smuzhiyun struct iommu_map_table *iommu, 44*4882a593Smuzhiyun unsigned long npages, 45*4882a593Smuzhiyun unsigned long *handle, 46*4882a593Smuzhiyun unsigned long mask, 47*4882a593Smuzhiyun unsigned int align_order); 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun extern void iommu_tbl_range_free(struct iommu_map_table *iommu, 50*4882a593Smuzhiyun u64 dma_addr, unsigned long npages, 51*4882a593Smuzhiyun unsigned long entry); 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #endif 54