1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* io-unit.h: Definitions for the sun4d IO-UNIT. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _SPARC_IO_UNIT_H 7*4882a593Smuzhiyun #define _SPARC_IO_UNIT_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/spinlock.h> 10*4882a593Smuzhiyun #include <linux/pgtable.h> 11*4882a593Smuzhiyun #include <asm/page.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* The io-unit handles all virtual to physical address translations 14*4882a593Smuzhiyun * that occur between the SBUS and physical memory. Access by 15*4882a593Smuzhiyun * the cpu to IO registers and similar go over the xdbus so are 16*4882a593Smuzhiyun * translated by the on chip SRMMU. The io-unit and the srmmu do 17*4882a593Smuzhiyun * not need to have the same translations at all, in fact most 18*4882a593Smuzhiyun * of the time the translations they handle are a disjunct set. 19*4882a593Smuzhiyun * Basically the io-unit handles all dvma sbus activity. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* AIEEE, unlike the nice sun4m, these monsters have 23*4882a593Smuzhiyun fixed DMA range 64M */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define IOUNIT_DMA_BASE 0xfc000000 /* TOP - 64M */ 26*4882a593Smuzhiyun #define IOUNIT_DMA_SIZE 0x04000000 /* 64M */ 27*4882a593Smuzhiyun /* We use last 1M for sparc_dvma_malloc */ 28*4882a593Smuzhiyun #define IOUNIT_DVMA_SIZE 0x00100000 /* 1M */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* The format of an iopte in the external page tables */ 31*4882a593Smuzhiyun #define IOUPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */ 32*4882a593Smuzhiyun #define IOUPTE_CACHE 0x00000080 /* Cached (in Viking/MXCC) */ 33*4882a593Smuzhiyun /* XXX Jakub, find out how to program SBUS streaming cache on XDBUS/sun4d. 34*4882a593Smuzhiyun * XXX Actually, all you should need to do is find out where the registers 35*4882a593Smuzhiyun * XXX are and copy over the sparc64 implementation I wrote. There may be 36*4882a593Smuzhiyun * XXX some horrible hwbugs though, so be careful. -DaveM 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun #define IOUPTE_STREAM 0x00000040 /* Translation can use streaming cache */ 39*4882a593Smuzhiyun #define IOUPTE_INTRA 0x00000008 /* SBUS direct slot->slot transfer */ 40*4882a593Smuzhiyun #define IOUPTE_WRITE 0x00000004 /* Writeable */ 41*4882a593Smuzhiyun #define IOUPTE_VALID 0x00000002 /* IOPTE is valid */ 42*4882a593Smuzhiyun #define IOUPTE_PARITY 0x00000001 /* Parity is checked during DVMA */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun struct iounit_struct { 45*4882a593Smuzhiyun unsigned long bmap[(IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 3)) / sizeof(unsigned long)]; 46*4882a593Smuzhiyun spinlock_t lock; 47*4882a593Smuzhiyun iopte_t __iomem *page_table; 48*4882a593Smuzhiyun unsigned long rotor[3]; 49*4882a593Smuzhiyun unsigned long limit[4]; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define IOUNIT_BMAP1_START 0x00000000 53*4882a593Smuzhiyun #define IOUNIT_BMAP1_END (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 1)) 54*4882a593Smuzhiyun #define IOUNIT_BMAP2_START IOUNIT_BMAP1_END 55*4882a593Smuzhiyun #define IOUNIT_BMAP2_END IOUNIT_BMAP2_START + (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 2)) 56*4882a593Smuzhiyun #define IOUNIT_BMAPM_START IOUNIT_BMAP2_END 57*4882a593Smuzhiyun #define IOUNIT_BMAPM_END ((IOUNIT_DMA_SIZE - IOUNIT_DVMA_SIZE) >> PAGE_SHIFT) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #endif /* !(_SPARC_IO_UNIT_H) */ 60