1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _SPARC64_ESTATE_H 3*4882a593Smuzhiyun #define _SPARC64_ESTATE_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* UltraSPARC-III E-cache Error Enable */ 6*4882a593Smuzhiyun #define ESTATE_ERROR_FMT 0x0000000000040000 /* Force MTAG ECC */ 7*4882a593Smuzhiyun #define ESTATE_ERROR_FMESS 0x000000000003c000 /* Forced MTAG ECC val */ 8*4882a593Smuzhiyun #define ESTATE_ERROR_FMD 0x0000000000002000 /* Force DATA ECC */ 9*4882a593Smuzhiyun #define ESTATE_ERROR_FDECC 0x0000000000001ff0 /* Forced DATA ECC val */ 10*4882a593Smuzhiyun #define ESTATE_ERROR_UCEEN 0x0000000000000008 /* See below */ 11*4882a593Smuzhiyun #define ESTATE_ERROR_NCEEN 0x0000000000000002 /* See below */ 12*4882a593Smuzhiyun #define ESTATE_ERROR_CEEN 0x0000000000000001 /* See below */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* UCEEN enables the fast_ECC_error trap for: 1) software correctable E-cache 15*4882a593Smuzhiyun * errors 2) uncorrectable E-cache errors. Such events only occur on reads 16*4882a593Smuzhiyun * of the E-cache by the local processor for: 1) data loads 2) instruction 17*4882a593Smuzhiyun * fetches 3) atomic operations. Such events _cannot_ occur for: 1) merge 18*4882a593Smuzhiyun * 2) writeback 2) copyout. The AFSR bits associated with these traps are 19*4882a593Smuzhiyun * UCC and UCU. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* NCEEN enables instruction_access_error, data_access_error, and ECC_error traps 23*4882a593Smuzhiyun * for uncorrectable ECC errors and system errors. 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * Uncorrectable system bus data error or MTAG ECC error, system bus TimeOUT, 26*4882a593Smuzhiyun * or system bus BusERR: 27*4882a593Smuzhiyun * 1) As the result of an instruction fetch, will generate instruction_access_error 28*4882a593Smuzhiyun * 2) As the result of a load etc. will generate data_access_error. 29*4882a593Smuzhiyun * 3) As the result of store merge completion, writeback, or copyout will 30*4882a593Smuzhiyun * generate a disrupting ECC_error trap. 31*4882a593Smuzhiyun * 4) As the result of such errors on instruction vector fetch can generate any 32*4882a593Smuzhiyun * of the 3 trap types. 33*4882a593Smuzhiyun * 34*4882a593Smuzhiyun * The AFSR bits associated with these traps are EMU, EDU, WDU, CPU, IVU, UE, 35*4882a593Smuzhiyun * BERR, and TO. 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* CEEN enables the ECC_error trap for hardware corrected ECC errors. System bus 39*4882a593Smuzhiyun * reads resulting in a hardware corrected data or MTAG ECC error will generate an 40*4882a593Smuzhiyun * ECC_error disrupting trap with this bit enabled. 41*4882a593Smuzhiyun * 42*4882a593Smuzhiyun * This same trap will also be generated when a hardware corrected ECC error results 43*4882a593Smuzhiyun * during store merge, writeback, and copyout operations. 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* In general, if the trap enable bits above are disabled the AFSR bits will still 47*4882a593Smuzhiyun * log the events even though the trap will not be generated by the processor. 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif /* _SPARC64_ESTATE_H */ 51