1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ecc.h: Definitions and defines for the external cache/memory 4*4882a593Smuzhiyun * controller on the sun4m. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _SPARC_ECC_H 10*4882a593Smuzhiyun #define _SPARC_ECC_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* These registers are accessed through the SRMMU passthrough ASI 0x20 */ 13*4882a593Smuzhiyun #define ECC_ENABLE 0x00000000 /* ECC enable register */ 14*4882a593Smuzhiyun #define ECC_FSTATUS 0x00000008 /* ECC fault status register */ 15*4882a593Smuzhiyun #define ECC_FADDR 0x00000010 /* ECC fault address register */ 16*4882a593Smuzhiyun #define ECC_DIGNOSTIC 0x00000018 /* ECC diagnostics register */ 17*4882a593Smuzhiyun #define ECC_MBAENAB 0x00000020 /* MBus arbiter enable register */ 18*4882a593Smuzhiyun #define ECC_DMESG 0x00001000 /* Diagnostic message passing area */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* ECC MBus Arbiter Enable register: 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * ---------------------------------------- 23*4882a593Smuzhiyun * | |SBUS|MOD3|MOD2|MOD1|RSV| 24*4882a593Smuzhiyun * ---------------------------------------- 25*4882a593Smuzhiyun * 31 5 4 3 2 1 0 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * SBUS: Enable MBus Arbiter on the SBus 0=off 1=on 28*4882a593Smuzhiyun * MOD3: Enable MBus Arbiter on MBus module 3 0=off 1=on 29*4882a593Smuzhiyun * MOD2: Enable MBus Arbiter on MBus module 2 0=off 1=on 30*4882a593Smuzhiyun * MOD1: Enable MBus Arbiter on MBus module 1 0=off 1=on 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define ECC_MBAE_SBUS 0x00000010 34*4882a593Smuzhiyun #define ECC_MBAE_MOD3 0x00000008 35*4882a593Smuzhiyun #define ECC_MBAE_MOD2 0x00000004 36*4882a593Smuzhiyun #define ECC_MBAE_MOD1 0x00000002 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* ECC Fault Control Register layout: 39*4882a593Smuzhiyun * 40*4882a593Smuzhiyun * ----------------------------- 41*4882a593Smuzhiyun * | RESV | ECHECK | EINT | 42*4882a593Smuzhiyun * ----------------------------- 43*4882a593Smuzhiyun * 31 2 1 0 44*4882a593Smuzhiyun * 45*4882a593Smuzhiyun * ECHECK: Enable ECC checking. 0=off 1=on 46*4882a593Smuzhiyun * EINT: Enable Interrupts for correctable errors. 0=off 1=on 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun #define ECC_FCR_CHECK 0x00000002 49*4882a593Smuzhiyun #define ECC_FCR_INTENAB 0x00000001 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* ECC Fault Address Register Zero layout: 52*4882a593Smuzhiyun * 53*4882a593Smuzhiyun * ----------------------------------------------------- 54*4882a593Smuzhiyun * | MID | S | RSV | VA | BM |AT| C| SZ |TYP| PADDR | 55*4882a593Smuzhiyun * ----------------------------------------------------- 56*4882a593Smuzhiyun * 31-28 27 26-22 21-14 13 12 11 10-8 7-4 3-0 57*4882a593Smuzhiyun * 58*4882a593Smuzhiyun * MID: ModuleID of the faulting processor. ie. who did it? 59*4882a593Smuzhiyun * S: Supervisor/Privileged access? 0=no 1=yes 60*4882a593Smuzhiyun * VA: Bits 19-12 of the virtual faulting address, these are the 61*4882a593Smuzhiyun * superset bits in the virtual cache and can be used for 62*4882a593Smuzhiyun * a flush operation if necessary. 63*4882a593Smuzhiyun * BM: Boot mode? 0=no 1=yes This is just like the SRMMU boot 64*4882a593Smuzhiyun * mode bit. 65*4882a593Smuzhiyun * AT: Did this fault happen during an atomic instruction? 0=no 66*4882a593Smuzhiyun * 1=yes. This means either an 'ldstub' or 'swap' instruction 67*4882a593Smuzhiyun * was in progress (but not finished) when this fault happened. 68*4882a593Smuzhiyun * This indicated whether the bus was locked when the fault 69*4882a593Smuzhiyun * occurred. 70*4882a593Smuzhiyun * C: Did the pte for this access indicate that it was cacheable? 71*4882a593Smuzhiyun * 0=no 1=yes 72*4882a593Smuzhiyun * SZ: The size of the transaction. 73*4882a593Smuzhiyun * TYP: The transaction type. 74*4882a593Smuzhiyun * PADDR: Bits 35-32 of the physical address for the fault. 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun #define ECC_FADDR0_MIDMASK 0xf0000000 77*4882a593Smuzhiyun #define ECC_FADDR0_S 0x08000000 78*4882a593Smuzhiyun #define ECC_FADDR0_VADDR 0x003fc000 79*4882a593Smuzhiyun #define ECC_FADDR0_BMODE 0x00002000 80*4882a593Smuzhiyun #define ECC_FADDR0_ATOMIC 0x00001000 81*4882a593Smuzhiyun #define ECC_FADDR0_CACHE 0x00000800 82*4882a593Smuzhiyun #define ECC_FADDR0_SIZE 0x00000700 83*4882a593Smuzhiyun #define ECC_FADDR0_TYPE 0x000000f0 84*4882a593Smuzhiyun #define ECC_FADDR0_PADDR 0x0000000f 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* ECC Fault Address Register One layout: 87*4882a593Smuzhiyun * 88*4882a593Smuzhiyun * ------------------------------------- 89*4882a593Smuzhiyun * | Physical Address 31-0 | 90*4882a593Smuzhiyun * ------------------------------------- 91*4882a593Smuzhiyun * 31 0 92*4882a593Smuzhiyun * 93*4882a593Smuzhiyun * You get the upper 4 bits of the physical address from the 94*4882a593Smuzhiyun * PADDR field in ECC Fault Address Zero register. 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* ECC Fault Status Register layout: 98*4882a593Smuzhiyun * 99*4882a593Smuzhiyun * ---------------------------------------------- 100*4882a593Smuzhiyun * | RESV|C2E|MULT|SYNDROME|DWORD|UNC|TIMEO|BS|C| 101*4882a593Smuzhiyun * ---------------------------------------------- 102*4882a593Smuzhiyun * 31-18 17 16 15-8 7-4 3 2 1 0 103*4882a593Smuzhiyun * 104*4882a593Smuzhiyun * C2E: A C2 graphics error occurred. 0=no 1=yes (SS10 only) 105*4882a593Smuzhiyun * MULT: Multiple errors occurred ;-O 0=no 1=prom_panic(yes) 106*4882a593Smuzhiyun * SYNDROME: Controller is mentally unstable. 107*4882a593Smuzhiyun * DWORD: 108*4882a593Smuzhiyun * UNC: Uncorrectable error. 0=no 1=yes 109*4882a593Smuzhiyun * TIMEO: Timeout occurred. 0=no 1=yes 110*4882a593Smuzhiyun * BS: C2 graphics bad slot access. 0=no 1=yes (SS10 only) 111*4882a593Smuzhiyun * C: Correctable error? 0=no 1=yes 112*4882a593Smuzhiyun */ 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define ECC_FSR_C2ERR 0x00020000 115*4882a593Smuzhiyun #define ECC_FSR_MULT 0x00010000 116*4882a593Smuzhiyun #define ECC_FSR_SYND 0x0000ff00 117*4882a593Smuzhiyun #define ECC_FSR_DWORD 0x000000f0 118*4882a593Smuzhiyun #define ECC_FSR_UNC 0x00000008 119*4882a593Smuzhiyun #define ECC_FSR_TIMEO 0x00000004 120*4882a593Smuzhiyun #define ECC_FSR_BADSLOT 0x00000002 121*4882a593Smuzhiyun #define ECC_FSR_C 0x00000001 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #endif /* !(_SPARC_ECC_H) */ 124