1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _SPARC64_DCR_H 3*4882a593Smuzhiyun #define _SPARC64_DCR_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* UltraSparc-III/III+ Dispatch Control Register, ASR 0x12 */ 6*4882a593Smuzhiyun #define DCR_DPE 0x0000000000001000 /* III+: D$ Parity Error Enable */ 7*4882a593Smuzhiyun #define DCR_OBS 0x0000000000000fc0 /* Observability Bus Controls */ 8*4882a593Smuzhiyun #define DCR_BPE 0x0000000000000020 /* Branch Predict Enable */ 9*4882a593Smuzhiyun #define DCR_RPE 0x0000000000000010 /* Return Address Prediction Enable */ 10*4882a593Smuzhiyun #define DCR_SI 0x0000000000000008 /* Single Instruction Disable */ 11*4882a593Smuzhiyun #define DCR_IPE 0x0000000000000004 /* III+: I$ Parity Error Enable */ 12*4882a593Smuzhiyun #define DCR_IFPOE 0x0000000000000002 /* IRQ FP Operation Enable */ 13*4882a593Smuzhiyun #define DCR_MS 0x0000000000000001 /* Multi-Scalar dispatch */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #endif /* _SPARC64_DCR_H */ 16