1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _SPARC_CACHEFLUSH_H 3*4882a593Smuzhiyun #define _SPARC_CACHEFLUSH_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <asm/cachetlb_32.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define flush_cache_all() \ 8*4882a593Smuzhiyun sparc32_cachetlb_ops->cache_all() 9*4882a593Smuzhiyun #define flush_cache_mm(mm) \ 10*4882a593Smuzhiyun sparc32_cachetlb_ops->cache_mm(mm) 11*4882a593Smuzhiyun #define flush_cache_dup_mm(mm) \ 12*4882a593Smuzhiyun sparc32_cachetlb_ops->cache_mm(mm) 13*4882a593Smuzhiyun #define flush_cache_range(vma,start,end) \ 14*4882a593Smuzhiyun sparc32_cachetlb_ops->cache_range(vma, start, end) 15*4882a593Smuzhiyun #define flush_cache_page(vma,addr,pfn) \ 16*4882a593Smuzhiyun sparc32_cachetlb_ops->cache_page(vma, addr) 17*4882a593Smuzhiyun #define flush_icache_range(start, end) do { } while (0) 18*4882a593Smuzhiyun #define flush_icache_page(vma, pg) do { } while (0) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ 21*4882a593Smuzhiyun do { \ 22*4882a593Smuzhiyun flush_cache_page(vma, vaddr, page_to_pfn(page));\ 23*4882a593Smuzhiyun memcpy(dst, src, len); \ 24*4882a593Smuzhiyun } while (0) 25*4882a593Smuzhiyun #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ 26*4882a593Smuzhiyun do { \ 27*4882a593Smuzhiyun flush_cache_page(vma, vaddr, page_to_pfn(page));\ 28*4882a593Smuzhiyun memcpy(dst, src, len); \ 29*4882a593Smuzhiyun } while (0) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define __flush_page_to_ram(addr) \ 32*4882a593Smuzhiyun sparc32_cachetlb_ops->page_to_ram(addr) 33*4882a593Smuzhiyun #define flush_sig_insns(mm,insn_addr) \ 34*4882a593Smuzhiyun sparc32_cachetlb_ops->sig_insns(mm, insn_addr) 35*4882a593Smuzhiyun #define flush_page_for_dma(addr) \ 36*4882a593Smuzhiyun sparc32_cachetlb_ops->page_for_dma(addr) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun void sparc_flush_page_to_ram(struct page *page); 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 41*4882a593Smuzhiyun #define flush_dcache_page(page) sparc_flush_page_to_ram(page) 42*4882a593Smuzhiyun #define flush_dcache_mmap_lock(mapping) do { } while (0) 43*4882a593Smuzhiyun #define flush_dcache_mmap_unlock(mapping) do { } while (0) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define flush_cache_vmap(start, end) flush_cache_all() 46*4882a593Smuzhiyun #define flush_cache_vunmap(start, end) flush_cache_all() 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* When a context switch happens we must flush all user windows so that 49*4882a593Smuzhiyun * the windows of the current process are flushed onto its stack. This 50*4882a593Smuzhiyun * way the windows are all clean for the next process and the stack 51*4882a593Smuzhiyun * frames are up to date. 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun void flush_user_windows(void); 54*4882a593Smuzhiyun void kill_user_windows(void); 55*4882a593Smuzhiyun void flushw_all(void); 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #endif /* _SPARC_CACHEFLUSH_H */ 58