1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _SPARC_ASM_H 3*4882a593Smuzhiyun #define _SPARC_ASM_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* Macros to assist the sharing of assembler code between 32-bit and 6*4882a593Smuzhiyun * 64-bit sparc. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifdef CONFIG_SPARC64 10*4882a593Smuzhiyun #define BRANCH32(TYPE, PREDICT, DEST) \ 11*4882a593Smuzhiyun TYPE,PREDICT %icc, DEST 12*4882a593Smuzhiyun #define BRANCH32_ANNUL(TYPE, PREDICT, DEST) \ 13*4882a593Smuzhiyun TYPE,a,PREDICT %icc, DEST 14*4882a593Smuzhiyun #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ 15*4882a593Smuzhiyun brz,PREDICT REG, DEST 16*4882a593Smuzhiyun #define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \ 17*4882a593Smuzhiyun brz,a,PREDICT REG, DEST 18*4882a593Smuzhiyun #define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \ 19*4882a593Smuzhiyun brnz,PREDICT REG, DEST 20*4882a593Smuzhiyun #define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \ 21*4882a593Smuzhiyun brnz,a,PREDICT REG, DEST 22*4882a593Smuzhiyun #else 23*4882a593Smuzhiyun #define BRANCH32(TYPE, PREDICT, DEST) \ 24*4882a593Smuzhiyun TYPE DEST 25*4882a593Smuzhiyun #define BRANCH32_ANNUL(TYPE, PREDICT, DEST) \ 26*4882a593Smuzhiyun TYPE,a DEST 27*4882a593Smuzhiyun #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ 28*4882a593Smuzhiyun cmp REG, 0; \ 29*4882a593Smuzhiyun be DEST 30*4882a593Smuzhiyun #define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \ 31*4882a593Smuzhiyun cmp REG, 0; \ 32*4882a593Smuzhiyun be,a DEST 33*4882a593Smuzhiyun #define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \ 34*4882a593Smuzhiyun cmp REG, 0; \ 35*4882a593Smuzhiyun bne DEST 36*4882a593Smuzhiyun #define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \ 37*4882a593Smuzhiyun cmp REG, 0; \ 38*4882a593Smuzhiyun bne,a DEST 39*4882a593Smuzhiyun #endif 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #endif /* _SPARC_ASM_H */ 42