1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * apb.h: Advanced PCI Bridge Configuration Registers and Bits 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _SPARC64_APB_H 9*4882a593Smuzhiyun #define _SPARC64_APB_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define APB_TICK_REGISTER 0xb0 12*4882a593Smuzhiyun #define APB_INT_ACK 0xb8 13*4882a593Smuzhiyun #define APB_PRIMARY_MASTER_RETRY_LIMIT 0xc0 14*4882a593Smuzhiyun #define APB_DMA_ASFR 0xc8 15*4882a593Smuzhiyun #define APB_DMA_AFAR 0xd0 16*4882a593Smuzhiyun #define APB_PIO_TARGET_RETRY_LIMIT 0xd8 17*4882a593Smuzhiyun #define APB_PIO_TARGET_LATENCY_TIMER 0xd9 18*4882a593Smuzhiyun #define APB_DMA_TARGET_RETRY_LIMIT 0xda 19*4882a593Smuzhiyun #define APB_DMA_TARGET_LATENCY_TIMER 0xdb 20*4882a593Smuzhiyun #define APB_SECONDARY_MASTER_RETRY_LIMIT 0xdc 21*4882a593Smuzhiyun #define APB_SECONDARY_CONTROL 0xdd 22*4882a593Smuzhiyun #define APB_IO_ADDRESS_MAP 0xde 23*4882a593Smuzhiyun #define APB_MEM_ADDRESS_MAP 0xdf 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define APB_PCI_CONTROL_LOW 0xe0 26*4882a593Smuzhiyun # define APB_PCI_CTL_LOW_ARB_PARK (1 << 21) 27*4882a593Smuzhiyun # define APB_PCI_CTL_LOW_ERRINT_EN (1 << 8) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define APB_PCI_CONTROL_HIGH 0xe4 30*4882a593Smuzhiyun # define APB_PCI_CTL_HIGH_SERR (1 << 2) 31*4882a593Smuzhiyun # define APB_PCI_CTL_HIGH_ARBITER_EN (1 << 0) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define APB_PIO_ASFR 0xe8 34*4882a593Smuzhiyun #define APB_PIO_AFAR 0xf0 35*4882a593Smuzhiyun #define APB_DIAG_REGISTER 0xf8 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #endif /* !(_SPARC64_APB_H) */ 38