1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * arch/sh/mm/tlb-urb.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * TLB entry wiring helpers for URB-equipped parts.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2010 Matt Fleming
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
9*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
10*4882a593Smuzhiyun * for more details.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun #include <linux/mm.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <asm/tlb.h>
15*4882a593Smuzhiyun #include <asm/mmu_context.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun * Load the entry for 'addr' into the TLB and wire the entry.
19*4882a593Smuzhiyun */
tlb_wire_entry(struct vm_area_struct * vma,unsigned long addr,pte_t pte)20*4882a593Smuzhiyun void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun unsigned long status, flags;
23*4882a593Smuzhiyun int urb;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun local_irq_save(flags);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun status = __raw_readl(MMUCR);
28*4882a593Smuzhiyun urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
29*4882a593Smuzhiyun status &= ~MMUCR_URC;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * Make sure we're not trying to wire the last TLB entry slot.
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun BUG_ON(!--urb);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun urb = urb % MMUCR_URB_NENTRIES;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun * Insert this entry into the highest non-wired TLB slot (via
40*4882a593Smuzhiyun * the URC field).
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun status |= (urb << MMUCR_URC_SHIFT);
43*4882a593Smuzhiyun __raw_writel(status, MMUCR);
44*4882a593Smuzhiyun ctrl_barrier();
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Load the entry into the TLB */
47*4882a593Smuzhiyun __update_tlb(vma, addr, pte);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* ... and wire it up. */
50*4882a593Smuzhiyun status = __raw_readl(MMUCR);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun status &= ~MMUCR_URB;
53*4882a593Smuzhiyun status |= (urb << MMUCR_URB_SHIFT);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun __raw_writel(status, MMUCR);
56*4882a593Smuzhiyun ctrl_barrier();
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun local_irq_restore(flags);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /*
62*4882a593Smuzhiyun * Unwire the last wired TLB entry.
63*4882a593Smuzhiyun *
64*4882a593Smuzhiyun * It should also be noted that it is not possible to wire and unwire
65*4882a593Smuzhiyun * TLB entries in an arbitrary order. If you wire TLB entry N, followed
66*4882a593Smuzhiyun * by entry N+1, you must unwire entry N+1 first, then entry N. In this
67*4882a593Smuzhiyun * respect, it works like a stack or LIFO queue.
68*4882a593Smuzhiyun */
tlb_unwire_entry(void)69*4882a593Smuzhiyun void tlb_unwire_entry(void)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun unsigned long status, flags;
72*4882a593Smuzhiyun int urb;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun local_irq_save(flags);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun status = __raw_readl(MMUCR);
77*4882a593Smuzhiyun urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
78*4882a593Smuzhiyun status &= ~MMUCR_URB;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun * Make sure we're not trying to unwire a TLB entry when none
82*4882a593Smuzhiyun * have been wired.
83*4882a593Smuzhiyun */
84*4882a593Smuzhiyun BUG_ON(urb++ == MMUCR_URB_NENTRIES);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun urb = urb % MMUCR_URB_NENTRIES;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun status |= (urb << MMUCR_URB_SHIFT);
89*4882a593Smuzhiyun __raw_writel(status, MMUCR);
90*4882a593Smuzhiyun ctrl_barrier();
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun local_irq_restore(flags);
93*4882a593Smuzhiyun }
94