1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/sh/mm/tlb-sh4.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SH-4 specific TLB operations
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 1999 Niibe Yutaka
8*4882a593Smuzhiyun * Copyright (C) 2002 - 2007 Paul Mundt
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/mm.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <asm/mmu_context.h>
14*4882a593Smuzhiyun #include <asm/cacheflush.h>
15*4882a593Smuzhiyun
__update_tlb(struct vm_area_struct * vma,unsigned long address,pte_t pte)16*4882a593Smuzhiyun void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun unsigned long flags, pteval, vpn;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * Handle debugger faulting in for debugee.
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun if (vma && current->active_mm != vma->vm_mm)
24*4882a593Smuzhiyun return;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun local_irq_save(flags);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* Set PTEH register */
29*4882a593Smuzhiyun vpn = (address & MMU_VPN_MASK) | get_asid();
30*4882a593Smuzhiyun __raw_writel(vpn, MMU_PTEH);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun pteval = pte.pte_low;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* Set PTEA register */
35*4882a593Smuzhiyun #ifdef CONFIG_X2TLB
36*4882a593Smuzhiyun /*
37*4882a593Smuzhiyun * For the extended mode TLB this is trivial, only the ESZ and
38*4882a593Smuzhiyun * EPR bits need to be written out to PTEA, with the remainder of
39*4882a593Smuzhiyun * the protection bits (with the exception of the compat-mode SZ
40*4882a593Smuzhiyun * and PR bits, which are cleared) being written out in PTEL.
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun __raw_writel(pte.pte_high, MMU_PTEA);
43*4882a593Smuzhiyun #else
44*4882a593Smuzhiyun if (cpu_data->flags & CPU_HAS_PTEA) {
45*4882a593Smuzhiyun /* The last 3 bits and the first one of pteval contains
46*4882a593Smuzhiyun * the PTEA timing control and space attribute bits
47*4882a593Smuzhiyun */
48*4882a593Smuzhiyun __raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun #endif
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* Set PTEL register */
53*4882a593Smuzhiyun pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
54*4882a593Smuzhiyun #ifdef CONFIG_CACHE_WRITETHROUGH
55*4882a593Smuzhiyun pteval |= _PAGE_WT;
56*4882a593Smuzhiyun #endif
57*4882a593Smuzhiyun /* conveniently, we want all the software flags to be 0 anyway */
58*4882a593Smuzhiyun __raw_writel(pteval, MMU_PTEL);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Load the TLB */
61*4882a593Smuzhiyun asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
62*4882a593Smuzhiyun local_irq_restore(flags);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
local_flush_tlb_one(unsigned long asid,unsigned long page)65*4882a593Smuzhiyun void local_flush_tlb_one(unsigned long asid, unsigned long page)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun unsigned long addr, data;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /*
70*4882a593Smuzhiyun * NOTE: PTEH.ASID should be set to this MM
71*4882a593Smuzhiyun * _AND_ we need to write ASID to the array.
72*4882a593Smuzhiyun *
73*4882a593Smuzhiyun * It would be simple if we didn't need to set PTEH.ASID...
74*4882a593Smuzhiyun */
75*4882a593Smuzhiyun addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
76*4882a593Smuzhiyun data = page | asid; /* VALID bit is off */
77*4882a593Smuzhiyun jump_to_uncached();
78*4882a593Smuzhiyun __raw_writel(data, addr);
79*4882a593Smuzhiyun back_to_cached();
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
local_flush_tlb_all(void)82*4882a593Smuzhiyun void local_flush_tlb_all(void)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun unsigned long flags, status;
85*4882a593Smuzhiyun int i;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /*
88*4882a593Smuzhiyun * Flush all the TLB.
89*4882a593Smuzhiyun */
90*4882a593Smuzhiyun local_irq_save(flags);
91*4882a593Smuzhiyun jump_to_uncached();
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun status = __raw_readl(MMUCR);
94*4882a593Smuzhiyun status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun if (status == 0)
97*4882a593Smuzhiyun status = MMUCR_URB_NENTRIES;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun for (i = 0; i < status; i++)
100*4882a593Smuzhiyun __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun for (i = 0; i < 4; i++)
103*4882a593Smuzhiyun __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun back_to_cached();
106*4882a593Smuzhiyun ctrl_barrier();
107*4882a593Smuzhiyun local_irq_restore(flags);
108*4882a593Smuzhiyun }
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