1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/sh/mm/tlb-sh3.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SH-3 specific TLB operations
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 1999 Niibe Yutaka
8*4882a593Smuzhiyun * Copyright (C) 2002 Paul Mundt
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #include <linux/signal.h>
11*4882a593Smuzhiyun #include <linux/sched.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/errno.h>
14*4882a593Smuzhiyun #include <linux/string.h>
15*4882a593Smuzhiyun #include <linux/types.h>
16*4882a593Smuzhiyun #include <linux/ptrace.h>
17*4882a593Smuzhiyun #include <linux/mman.h>
18*4882a593Smuzhiyun #include <linux/mm.h>
19*4882a593Smuzhiyun #include <linux/smp.h>
20*4882a593Smuzhiyun #include <linux/interrupt.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <asm/io.h>
23*4882a593Smuzhiyun #include <linux/uaccess.h>
24*4882a593Smuzhiyun #include <asm/mmu_context.h>
25*4882a593Smuzhiyun #include <asm/cacheflush.h>
26*4882a593Smuzhiyun
__update_tlb(struct vm_area_struct * vma,unsigned long address,pte_t pte)27*4882a593Smuzhiyun void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun unsigned long flags, pteval, vpn;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * Handle debugger faulting in for debugee.
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun if (vma && current->active_mm != vma->vm_mm)
35*4882a593Smuzhiyun return;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun local_irq_save(flags);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Set PTEH register */
40*4882a593Smuzhiyun vpn = (address & MMU_VPN_MASK) | get_asid();
41*4882a593Smuzhiyun __raw_writel(vpn, MMU_PTEH);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun pteval = pte_val(pte);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* Set PTEL register */
46*4882a593Smuzhiyun pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
47*4882a593Smuzhiyun /* conveniently, we want all the software flags to be 0 anyway */
48*4882a593Smuzhiyun __raw_writel(pteval, MMU_PTEL);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* Load the TLB */
51*4882a593Smuzhiyun asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
52*4882a593Smuzhiyun local_irq_restore(flags);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
local_flush_tlb_one(unsigned long asid,unsigned long page)55*4882a593Smuzhiyun void local_flush_tlb_one(unsigned long asid, unsigned long page)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun unsigned long addr, data;
58*4882a593Smuzhiyun int i, ways = MMU_NTLB_WAYS;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun * NOTE: PTEH.ASID should be set to this MM
62*4882a593Smuzhiyun * _AND_ we need to write ASID to the array.
63*4882a593Smuzhiyun *
64*4882a593Smuzhiyun * It would be simple if we didn't need to set PTEH.ASID...
65*4882a593Smuzhiyun */
66*4882a593Smuzhiyun addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000);
67*4882a593Smuzhiyun data = (page & 0xfffe0000) | asid; /* VALID bit is off */
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) {
70*4882a593Smuzhiyun addr |= MMU_PAGE_ASSOC_BIT;
71*4882a593Smuzhiyun ways = 1; /* we already know the way .. */
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun for (i = 0; i < ways; i++)
75*4882a593Smuzhiyun __raw_writel(data, addr + (i << 8));
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
local_flush_tlb_all(void)78*4882a593Smuzhiyun void local_flush_tlb_all(void)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun unsigned long flags, status;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun * Flush all the TLB.
84*4882a593Smuzhiyun *
85*4882a593Smuzhiyun * Write to the MMU control register's bit:
86*4882a593Smuzhiyun * TF-bit for SH-3, TI-bit for SH-4.
87*4882a593Smuzhiyun * It's same position, bit #2.
88*4882a593Smuzhiyun */
89*4882a593Smuzhiyun local_irq_save(flags);
90*4882a593Smuzhiyun status = __raw_readl(MMUCR);
91*4882a593Smuzhiyun status |= 0x04;
92*4882a593Smuzhiyun __raw_writel(status, MMUCR);
93*4882a593Smuzhiyun ctrl_barrier();
94*4882a593Smuzhiyun local_irq_restore(flags);
95*4882a593Smuzhiyun }
96