1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * arch/sh/mm/tlb-pteaex.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * TLB operations for SH-X3 CPUs featuring PTE ASID Extensions.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2009 Paul Mundt
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
9*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
10*4882a593Smuzhiyun * for more details.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/mm.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <asm/mmu_context.h>
16*4882a593Smuzhiyun #include <asm/cacheflush.h>
17*4882a593Smuzhiyun
__update_tlb(struct vm_area_struct * vma,unsigned long address,pte_t pte)18*4882a593Smuzhiyun void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun unsigned long flags, pteval, vpn;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun * Handle debugger faulting in for debugee.
24*4882a593Smuzhiyun */
25*4882a593Smuzhiyun if (vma && current->active_mm != vma->vm_mm)
26*4882a593Smuzhiyun return;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun local_irq_save(flags);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* Set PTEH register */
31*4882a593Smuzhiyun vpn = address & MMU_VPN_MASK;
32*4882a593Smuzhiyun __raw_writel(vpn, MMU_PTEH);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* Set PTEAEX */
35*4882a593Smuzhiyun __raw_writel(get_asid(), MMU_PTEAEX);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun pteval = pte.pte_low;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Set PTEA register */
40*4882a593Smuzhiyun #ifdef CONFIG_X2TLB
41*4882a593Smuzhiyun /*
42*4882a593Smuzhiyun * For the extended mode TLB this is trivial, only the ESZ and
43*4882a593Smuzhiyun * EPR bits need to be written out to PTEA, with the remainder of
44*4882a593Smuzhiyun * the protection bits (with the exception of the compat-mode SZ
45*4882a593Smuzhiyun * and PR bits, which are cleared) being written out in PTEL.
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun __raw_writel(pte.pte_high, MMU_PTEA);
48*4882a593Smuzhiyun #endif
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* Set PTEL register */
51*4882a593Smuzhiyun pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
52*4882a593Smuzhiyun #ifdef CONFIG_CACHE_WRITETHROUGH
53*4882a593Smuzhiyun pteval |= _PAGE_WT;
54*4882a593Smuzhiyun #endif
55*4882a593Smuzhiyun /* conveniently, we want all the software flags to be 0 anyway */
56*4882a593Smuzhiyun __raw_writel(pteval, MMU_PTEL);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* Load the TLB */
59*4882a593Smuzhiyun asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
60*4882a593Smuzhiyun local_irq_restore(flags);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun * While SH-X2 extended TLB mode splits out the memory-mapped I/UTLB
65*4882a593Smuzhiyun * data arrays, SH-X3 cores with PTEAEX split out the memory-mapped
66*4882a593Smuzhiyun * address arrays. In compat mode the second array is inaccessible, while
67*4882a593Smuzhiyun * in extended mode, the legacy 8-bit ASID field in address array 1 has
68*4882a593Smuzhiyun * undefined behaviour.
69*4882a593Smuzhiyun */
local_flush_tlb_one(unsigned long asid,unsigned long page)70*4882a593Smuzhiyun void local_flush_tlb_one(unsigned long asid, unsigned long page)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun jump_to_uncached();
73*4882a593Smuzhiyun __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
74*4882a593Smuzhiyun __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
75*4882a593Smuzhiyun __raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
76*4882a593Smuzhiyun __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
77*4882a593Smuzhiyun back_to_cached();
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
local_flush_tlb_all(void)80*4882a593Smuzhiyun void local_flush_tlb_all(void)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun unsigned long flags, status;
83*4882a593Smuzhiyun int i;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /*
86*4882a593Smuzhiyun * Flush all the TLB.
87*4882a593Smuzhiyun */
88*4882a593Smuzhiyun local_irq_save(flags);
89*4882a593Smuzhiyun jump_to_uncached();
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun status = __raw_readl(MMUCR);
92*4882a593Smuzhiyun status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun if (status == 0)
95*4882a593Smuzhiyun status = MMUCR_URB_NENTRIES;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun for (i = 0; i < status; i++)
98*4882a593Smuzhiyun __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun for (i = 0; i < 4; i++)
101*4882a593Smuzhiyun __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun back_to_cached();
104*4882a593Smuzhiyun ctrl_barrier();
105*4882a593Smuzhiyun local_irq_restore(flags);
106*4882a593Smuzhiyun }
107