1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/sh/kernel/cpu/sh3/probe.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * CPU Subtype Probing for SH-3.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 1999, 2000 Niibe Yutaka
8*4882a593Smuzhiyun * Copyright (C) 2002 Paul Mundt
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <asm/processor.h>
13*4882a593Smuzhiyun #include <asm/cache.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun
cpu_probe(void)16*4882a593Smuzhiyun void cpu_probe(void)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun unsigned long addr0, addr1, data0, data1, data2, data3;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun jump_to_uncached();
21*4882a593Smuzhiyun /*
22*4882a593Smuzhiyun * Check if the entry shadows or not.
23*4882a593Smuzhiyun * When shadowed, it's 128-entry system.
24*4882a593Smuzhiyun * Otherwise, it's 256-entry system.
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun addr0 = CACHE_OC_ADDRESS_ARRAY + (3 << 12);
27*4882a593Smuzhiyun addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* First, write back & invalidate */
30*4882a593Smuzhiyun data0 = __raw_readl(addr0);
31*4882a593Smuzhiyun __raw_writel(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
32*4882a593Smuzhiyun data1 = __raw_readl(addr1);
33*4882a593Smuzhiyun __raw_writel(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Next, check if there's shadow or not */
36*4882a593Smuzhiyun data0 = __raw_readl(addr0);
37*4882a593Smuzhiyun data0 ^= SH_CACHE_VALID;
38*4882a593Smuzhiyun __raw_writel(data0, addr0);
39*4882a593Smuzhiyun data1 = __raw_readl(addr1);
40*4882a593Smuzhiyun data2 = data1 ^ SH_CACHE_VALID;
41*4882a593Smuzhiyun __raw_writel(data2, addr1);
42*4882a593Smuzhiyun data3 = __raw_readl(addr0);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* Lastly, invaliate them. */
45*4882a593Smuzhiyun __raw_writel(data0&~SH_CACHE_VALID, addr0);
46*4882a593Smuzhiyun __raw_writel(data2&~SH_CACHE_VALID, addr1);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun back_to_cached();
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun boot_cpu_data.dcache.ways = 4;
51*4882a593Smuzhiyun boot_cpu_data.dcache.entry_shift = 4;
52*4882a593Smuzhiyun boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
53*4882a593Smuzhiyun boot_cpu_data.dcache.flags = 0;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * 7709A/7729 has 16K cache (256-entry), while 7702 has only
57*4882a593Smuzhiyun * 2K(direct) 7702 is not supported (yet)
58*4882a593Smuzhiyun */
59*4882a593Smuzhiyun if (data0 == data1 && data2 == data3) { /* Shadow */
60*4882a593Smuzhiyun boot_cpu_data.dcache.way_incr = (1 << 11);
61*4882a593Smuzhiyun boot_cpu_data.dcache.entry_mask = 0x7f0;
62*4882a593Smuzhiyun boot_cpu_data.dcache.sets = 128;
63*4882a593Smuzhiyun boot_cpu_data.type = CPU_SH7708;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun boot_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC;
66*4882a593Smuzhiyun } else { /* 7709A or 7729 */
67*4882a593Smuzhiyun boot_cpu_data.dcache.way_incr = (1 << 12);
68*4882a593Smuzhiyun boot_cpu_data.dcache.entry_mask = 0xff0;
69*4882a593Smuzhiyun boot_cpu_data.dcache.sets = 256;
70*4882a593Smuzhiyun boot_cpu_data.type = CPU_SH7729;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7706)
73*4882a593Smuzhiyun boot_cpu_data.type = CPU_SH7706;
74*4882a593Smuzhiyun #endif
75*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7710)
76*4882a593Smuzhiyun boot_cpu_data.type = CPU_SH7710;
77*4882a593Smuzhiyun #endif
78*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7712)
79*4882a593Smuzhiyun boot_cpu_data.type = CPU_SH7712;
80*4882a593Smuzhiyun #endif
81*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7720)
82*4882a593Smuzhiyun boot_cpu_data.type = CPU_SH7720;
83*4882a593Smuzhiyun #endif
84*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7721)
85*4882a593Smuzhiyun boot_cpu_data.type = CPU_SH7721;
86*4882a593Smuzhiyun #endif
87*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7705)
88*4882a593Smuzhiyun boot_cpu_data.type = CPU_SH7705;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun #if defined(CONFIG_SH7705_CACHE_32KB)
91*4882a593Smuzhiyun boot_cpu_data.dcache.way_incr = (1 << 13);
92*4882a593Smuzhiyun boot_cpu_data.dcache.entry_mask = 0x1ff0;
93*4882a593Smuzhiyun boot_cpu_data.dcache.sets = 512;
94*4882a593Smuzhiyun __raw_writel(CCR_CACHE_32KB, CCR3_REG);
95*4882a593Smuzhiyun #else
96*4882a593Smuzhiyun __raw_writel(CCR_CACHE_16KB, CCR3_REG);
97*4882a593Smuzhiyun #endif
98*4882a593Smuzhiyun #endif
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /*
102*4882a593Smuzhiyun * SH-3 doesn't have separate caches
103*4882a593Smuzhiyun */
104*4882a593Smuzhiyun boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
105*4882a593Smuzhiyun boot_cpu_data.icache = boot_cpu_data.dcache;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun boot_cpu_data.family = CPU_FAMILY_SH3;
108*4882a593Smuzhiyun }
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