1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/sh/kernel/cpu/sh3/clock-sh7706.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SH7706 support for the clock framework
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2006 Takashi YOSHII
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Based on arch/sh/kernel/cpu/sh3/clock-sh7709.c
10*4882a593Smuzhiyun * Copyright (C) 2005 Andriy Skulysh
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <asm/clock.h>
15*4882a593Smuzhiyun #include <asm/freq.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static int stc_multipliers[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
19*4882a593Smuzhiyun static int ifc_divisors[] = { 1, 2, 4, 1, 3, 1, 1, 1 };
20*4882a593Smuzhiyun static int pfc_divisors[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
21*4882a593Smuzhiyun
master_clk_init(struct clk * clk)22*4882a593Smuzhiyun static void master_clk_init(struct clk *clk)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun int frqcr = __raw_readw(FRQCR);
25*4882a593Smuzhiyun int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun clk->rate *= pfc_divisors[idx];
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static struct sh_clk_ops sh7706_master_clk_ops = {
31*4882a593Smuzhiyun .init = master_clk_init,
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
module_clk_recalc(struct clk * clk)34*4882a593Smuzhiyun static unsigned long module_clk_recalc(struct clk *clk)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun int frqcr = __raw_readw(FRQCR);
37*4882a593Smuzhiyun int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun return clk->parent->rate / pfc_divisors[idx];
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun static struct sh_clk_ops sh7706_module_clk_ops = {
43*4882a593Smuzhiyun .recalc = module_clk_recalc,
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
bus_clk_recalc(struct clk * clk)46*4882a593Smuzhiyun static unsigned long bus_clk_recalc(struct clk *clk)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun int frqcr = __raw_readw(FRQCR);
49*4882a593Smuzhiyun int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return clk->parent->rate / stc_multipliers[idx];
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static struct sh_clk_ops sh7706_bus_clk_ops = {
55*4882a593Smuzhiyun .recalc = bus_clk_recalc,
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
cpu_clk_recalc(struct clk * clk)58*4882a593Smuzhiyun static unsigned long cpu_clk_recalc(struct clk *clk)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun int frqcr = __raw_readw(FRQCR);
61*4882a593Smuzhiyun int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return clk->parent->rate / ifc_divisors[idx];
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun static struct sh_clk_ops sh7706_cpu_clk_ops = {
67*4882a593Smuzhiyun .recalc = cpu_clk_recalc,
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun static struct sh_clk_ops *sh7706_clk_ops[] = {
71*4882a593Smuzhiyun &sh7706_master_clk_ops,
72*4882a593Smuzhiyun &sh7706_module_clk_ops,
73*4882a593Smuzhiyun &sh7706_bus_clk_ops,
74*4882a593Smuzhiyun &sh7706_cpu_clk_ops,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
arch_init_clk_ops(struct sh_clk_ops ** ops,int idx)77*4882a593Smuzhiyun void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun if (idx < ARRAY_SIZE(sh7706_clk_ops))
80*4882a593Smuzhiyun *ops = sh7706_clk_ops[idx];
81*4882a593Smuzhiyun }
82