1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_CPU_FEATURES_H 3*4882a593Smuzhiyun #define __ASM_SH_CPU_FEATURES_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * Processor flags 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Note: When adding a new flag, keep cpu_flags[] in 9*4882a593Smuzhiyun * arch/sh/kernel/setup.c in sync so symbolic name 10*4882a593Smuzhiyun * mapping of the processor flags has a chance of being 11*4882a593Smuzhiyun * reasonably accurate. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * These flags are also available through the ELF 14*4882a593Smuzhiyun * auxiliary vector as AT_HWCAP. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define CPU_HAS_FPU 0x0001 /* Hardware FPU support */ 17*4882a593Smuzhiyun #define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */ 18*4882a593Smuzhiyun #define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */ 19*4882a593Smuzhiyun #define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */ 20*4882a593Smuzhiyun #define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */ 21*4882a593Smuzhiyun #define CPU_HAS_PTEA 0x0020 /* PTEA register */ 22*4882a593Smuzhiyun #define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */ 23*4882a593Smuzhiyun #define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */ 24*4882a593Smuzhiyun #define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */ 25*4882a593Smuzhiyun #define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */ 26*4882a593Smuzhiyun #define CPU_HAS_CAS_L 0x0400 /* cas.l atomic compare-and-swap */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #endif /* __ASM_SH_CPU_FEATURES_H */ 29