1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_SE7780_H 3*4882a593Smuzhiyun #define __ASM_SH_SE7780_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * linux/include/asm-sh/se7780.h 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2006,2007 Nobuhiro Iwamatsu 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Hitachi UL SolutionEngine 7780 Support. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #include <linux/sh_intc.h> 13*4882a593Smuzhiyun #include <asm/addrspace.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Box specific addresses. */ 16*4882a593Smuzhiyun #define SE_AREA0_WIDTH 4 /* Area0: 32bit */ 17*4882a593Smuzhiyun #define PA_ROM 0xa0000000 /* EPROM */ 18*4882a593Smuzhiyun #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ 19*4882a593Smuzhiyun #define PA_FROM 0xa1000000 /* Flash-ROM */ 20*4882a593Smuzhiyun #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ 21*4882a593Smuzhiyun #define PA_EXT1 0xa4000000 22*4882a593Smuzhiyun #define PA_EXT1_SIZE 0x04000000 23*4882a593Smuzhiyun #define PA_SM501 PA_EXT1 /* Graphic IC (SM501) */ 24*4882a593Smuzhiyun #define PA_SM501_SIZE PA_EXT1_SIZE /* Graphic IC (SM501) */ 25*4882a593Smuzhiyun #define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */ 26*4882a593Smuzhiyun #define PA_SDRAM_SIZE 0x08000000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define PA_EXT4 0xb0000000 29*4882a593Smuzhiyun #define PA_EXT4_SIZE 0x04000000 30*4882a593Smuzhiyun #define PA_EXT_FLASH PA_EXT4 /* Expansion Flash-ROM */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define PA_PERIPHERAL PA_AREA6_IO /* SW6-6=ON */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define PA_LAN (PA_PERIPHERAL + 0) /* SMC LAN91C111 */ 35*4882a593Smuzhiyun #define PA_LED_DISP (PA_PERIPHERAL + 0x02000000) /* 8words LED Display */ 36*4882a593Smuzhiyun #define DISP_CHAR_RAM (7 << 3) 37*4882a593Smuzhiyun #define DISP_SEL0_ADDR (DISP_CHAR_RAM + 0) 38*4882a593Smuzhiyun #define DISP_SEL1_ADDR (DISP_CHAR_RAM + 1) 39*4882a593Smuzhiyun #define DISP_SEL2_ADDR (DISP_CHAR_RAM + 2) 40*4882a593Smuzhiyun #define DISP_SEL3_ADDR (DISP_CHAR_RAM + 3) 41*4882a593Smuzhiyun #define DISP_SEL4_ADDR (DISP_CHAR_RAM + 4) 42*4882a593Smuzhiyun #define DISP_SEL5_ADDR (DISP_CHAR_RAM + 5) 43*4882a593Smuzhiyun #define DISP_SEL6_ADDR (DISP_CHAR_RAM + 6) 44*4882a593Smuzhiyun #define DISP_SEL7_ADDR (DISP_CHAR_RAM + 7) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define DISP_UDC_RAM (5 << 3) 47*4882a593Smuzhiyun #define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* FPGA register address and bit */ 50*4882a593Smuzhiyun #define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */ 51*4882a593Smuzhiyun #define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */ 52*4882a593Smuzhiyun #define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */ 53*4882a593Smuzhiyun #define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */ 54*4882a593Smuzhiyun #define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */ 55*4882a593Smuzhiyun #define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */ 56*4882a593Smuzhiyun #define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */ 57*4882a593Smuzhiyun #define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */ 58*4882a593Smuzhiyun #define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */ 59*4882a593Smuzhiyun #define FPGA_INTSTS1 (PA_FPGA + 18) /* Interrupt status register 1 */ 60*4882a593Smuzhiyun #define FPGA_INTSTS2 (PA_FPGA + 20) /* Interrupt status register 2 */ 61*4882a593Smuzhiyun #define FPGA_REQSEL (PA_FPGA + 22) /* REQ/GNT select register */ 62*4882a593Smuzhiyun #define FPGA_DBG_LED (PA_FPGA + 32) /* Debug LED(D-LED[8:1] */ 63*4882a593Smuzhiyun #define PA_LED FPGA_DBG_LED 64*4882a593Smuzhiyun #define FPGA_IVDRID (PA_FPGA + 36) /* iVDR ID Register */ 65*4882a593Smuzhiyun #define FPGA_IVDRPW (PA_FPGA + 38) /* iVDR Power ON Register */ 66*4882a593Smuzhiyun #define FPGA_MMCID (PA_FPGA + 40) /* MMC ID Register */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* FPGA INTSEL position */ 69*4882a593Smuzhiyun /* INTSEL1 */ 70*4882a593Smuzhiyun #define IRQPOS_SMC91CX (0 * 4) 71*4882a593Smuzhiyun #define IRQPOS_SM501 (1 * 4) 72*4882a593Smuzhiyun /* INTSEL2 */ 73*4882a593Smuzhiyun #define IRQPOS_EXTINT1 (0 * 4) 74*4882a593Smuzhiyun #define IRQPOS_EXTINT2 (1 * 4) 75*4882a593Smuzhiyun #define IRQPOS_EXTINT3 (2 * 4) 76*4882a593Smuzhiyun #define IRQPOS_EXTINT4 (3 * 4) 77*4882a593Smuzhiyun /* INTSEL3 */ 78*4882a593Smuzhiyun #define IRQPOS_PCCPW (0 * 4) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* IDE interrupt */ 81*4882a593Smuzhiyun #define IRQ_IDE0 evt2irq(0xa60) /* iVDR */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* SMC interrupt */ 84*4882a593Smuzhiyun #define SMC_IRQ evt2irq(0x300) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* SM501 interrupt */ 87*4882a593Smuzhiyun #define SM501_IRQ evt2irq(0x200) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* interrupt pin */ 90*4882a593Smuzhiyun #define IRQPIN_EXTINT1 0 /* IRQ0 pin */ 91*4882a593Smuzhiyun #define IRQPIN_EXTINT2 1 /* IRQ1 pin */ 92*4882a593Smuzhiyun #define IRQPIN_EXTINT3 2 /* IRQ2 pin */ 93*4882a593Smuzhiyun #define IRQPIN_SMC91CX 3 /* IRQ3 pin */ 94*4882a593Smuzhiyun #define IRQPIN_EXTINT4 4 /* IRQ4 pin */ 95*4882a593Smuzhiyun #define IRQPIN_PCC0 5 /* IRQ5 pin */ 96*4882a593Smuzhiyun #define IRQPIN_PCC2 6 /* IRQ6 pin */ 97*4882a593Smuzhiyun #define IRQPIN_SM501 7 /* IRQ7 pin */ 98*4882a593Smuzhiyun #define IRQPIN_PCCPW 7 /* IRQ7 pin */ 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* arch/sh/boards/se/7780/irq.c */ 101*4882a593Smuzhiyun void init_se7780_IRQ(void); 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define __IO_PREFIX se7780 104*4882a593Smuzhiyun #include <asm/io_generic.h> 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #endif /* __ASM_SH_SE7780_H */ 107