1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_HITACHI_7751SE_H 3*4882a593Smuzhiyun #define __ASM_SH_HITACHI_7751SE_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * linux/include/asm-sh/hitachi_7751se.h 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2000 Kazumoto Kojima 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Hitachi SolutionEngine support 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun * Modified for 7751 Solution Engine by 13*4882a593Smuzhiyun * Ian da Silva and Jeremy Siegel, 2001. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #include <linux/sh_intc.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Box specific addresses. */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define PA_ROM 0x00000000 /* EPROM */ 20*4882a593Smuzhiyun #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ 21*4882a593Smuzhiyun #define PA_FROM 0x01000000 /* EPROM */ 22*4882a593Smuzhiyun #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ 23*4882a593Smuzhiyun #define PA_EXT1 0x04000000 24*4882a593Smuzhiyun #define PA_EXT1_SIZE 0x04000000 25*4882a593Smuzhiyun #define PA_EXT2 0x08000000 26*4882a593Smuzhiyun #define PA_EXT2_SIZE 0x04000000 27*4882a593Smuzhiyun #define PA_SDRAM 0x0c000000 28*4882a593Smuzhiyun #define PA_SDRAM_SIZE 0x04000000 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define PA_EXT4 0x12000000 31*4882a593Smuzhiyun #define PA_EXT4_SIZE 0x02000000 32*4882a593Smuzhiyun #define PA_EXT5 0x14000000 33*4882a593Smuzhiyun #define PA_EXT5_SIZE 0x04000000 34*4882a593Smuzhiyun #define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */ 37*4882a593Smuzhiyun #define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */ 38*4882a593Smuzhiyun #define PA_LED 0xba000000 /* LED */ 39*4882a593Smuzhiyun #define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ 42*4882a593Smuzhiyun #define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ 43*4882a593Smuzhiyun #define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ 44*4882a593Smuzhiyun #define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ 45*4882a593Smuzhiyun #define MRSHPC_MODE (PA_MRSHPC + 4) 46*4882a593Smuzhiyun #define MRSHPC_OPTION (PA_MRSHPC + 6) 47*4882a593Smuzhiyun #define MRSHPC_CSR (PA_MRSHPC + 8) 48*4882a593Smuzhiyun #define MRSHPC_ISR (PA_MRSHPC + 10) 49*4882a593Smuzhiyun #define MRSHPC_ICR (PA_MRSHPC + 12) 50*4882a593Smuzhiyun #define MRSHPC_CPWCR (PA_MRSHPC + 14) 51*4882a593Smuzhiyun #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) 52*4882a593Smuzhiyun #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) 53*4882a593Smuzhiyun #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) 54*4882a593Smuzhiyun #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) 55*4882a593Smuzhiyun #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) 56*4882a593Smuzhiyun #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) 57*4882a593Smuzhiyun #define MRSHPC_CDCR (PA_MRSHPC + 28) 58*4882a593Smuzhiyun #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define BCR_ILCRA (PA_BCR + 0) 61*4882a593Smuzhiyun #define BCR_ILCRB (PA_BCR + 2) 62*4882a593Smuzhiyun #define BCR_ILCRC (PA_BCR + 4) 63*4882a593Smuzhiyun #define BCR_ILCRD (PA_BCR + 6) 64*4882a593Smuzhiyun #define BCR_ILCRE (PA_BCR + 8) 65*4882a593Smuzhiyun #define BCR_ILCRF (PA_BCR + 10) 66*4882a593Smuzhiyun #define BCR_ILCRG (PA_BCR + 12) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define IRQ_79C973 evt2irq(0x3a0) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun void init_7751se_IRQ(void); 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define __IO_PREFIX sh7751se 73*4882a593Smuzhiyun #include <asm/io_generic.h> 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #endif /* __ASM_SH_HITACHI_7751SE_H */ 76