1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_SE7724_H 3*4882a593Smuzhiyun #define __ASM_SH_SE7724_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * linux/include/asm-sh/se7724.h 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2009 Renesas Solutions Corp. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Kuninori Morimoto <morimoto.kuninori@renesas.com> 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * Hitachi UL SolutionEngine 7724 Support. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * Based on se7722.h 15*4882a593Smuzhiyun * Copyright (C) 2007 Nobuhiro Iwamatsu 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #include <linux/sh_intc.h> 18*4882a593Smuzhiyun #include <asm/addrspace.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* SH Eth */ 21*4882a593Smuzhiyun #define SH_ETH_ADDR (0xA4600000) 22*4882a593Smuzhiyun #define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0) 23*4882a593Smuzhiyun #define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define PA_LED (0xba203000) /* 8bit LED */ 26*4882a593Smuzhiyun #define IRQ_MODE (0xba200010) 27*4882a593Smuzhiyun #define IRQ0_SR (0xba200014) 28*4882a593Smuzhiyun #define IRQ1_SR (0xba200018) 29*4882a593Smuzhiyun #define IRQ2_SR (0xba20001c) 30*4882a593Smuzhiyun #define IRQ0_MR (0xba200020) 31*4882a593Smuzhiyun #define IRQ1_MR (0xba200024) 32*4882a593Smuzhiyun #define IRQ2_MR (0xba200028) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* IRQ */ 35*4882a593Smuzhiyun #define IRQ0_IRQ evt2irq(0x600) 36*4882a593Smuzhiyun #define IRQ1_IRQ evt2irq(0x620) 37*4882a593Smuzhiyun #define IRQ2_IRQ evt2irq(0x640) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Bits in IRQ012 registers */ 40*4882a593Smuzhiyun #define SE7724_FPGA_IRQ_BASE 220 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* IRQ0 */ 43*4882a593Smuzhiyun #define IRQ0_BASE SE7724_FPGA_IRQ_BASE 44*4882a593Smuzhiyun #define IRQ0_KEY (IRQ0_BASE + 12) 45*4882a593Smuzhiyun #define IRQ0_RMII (IRQ0_BASE + 13) 46*4882a593Smuzhiyun #define IRQ0_SMC (IRQ0_BASE + 14) 47*4882a593Smuzhiyun #define IRQ0_MASK 0x7fff 48*4882a593Smuzhiyun #define IRQ0_END IRQ0_SMC 49*4882a593Smuzhiyun /* IRQ1 */ 50*4882a593Smuzhiyun #define IRQ1_BASE (IRQ0_END + 1) 51*4882a593Smuzhiyun #define IRQ1_TS (IRQ1_BASE + 0) 52*4882a593Smuzhiyun #define IRQ1_MASK 0x0001 53*4882a593Smuzhiyun #define IRQ1_END IRQ1_TS 54*4882a593Smuzhiyun /* IRQ2 */ 55*4882a593Smuzhiyun #define IRQ2_BASE (IRQ1_END + 1) 56*4882a593Smuzhiyun #define IRQ2_USB0 (IRQ1_BASE + 0) 57*4882a593Smuzhiyun #define IRQ2_USB1 (IRQ1_BASE + 1) 58*4882a593Smuzhiyun #define IRQ2_MASK 0x0003 59*4882a593Smuzhiyun #define IRQ2_END IRQ2_USB1 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define SE7724_FPGA_IRQ_NR (IRQ2_END - IRQ0_BASE) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* arch/sh/boards/se/7724/irq.c */ 64*4882a593Smuzhiyun void init_se7724_IRQ(void); 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define __IO_PREFIX se7724 67*4882a593Smuzhiyun #include <asm/io_generic.h> 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif /* __ASM_SH_SE7724_H */ 70