1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_SE7722_H 3*4882a593Smuzhiyun #define __ASM_SH_SE7722_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * linux/include/asm-sh/se7722.h 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2007 Nobuhiro Iwamatsu 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Hitachi UL SolutionEngine 7722 Support. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #include <linux/sh_intc.h> 13*4882a593Smuzhiyun #include <asm/addrspace.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Box specific addresses. */ 16*4882a593Smuzhiyun #define SE_AREA0_WIDTH 4 /* Area0: 32bit */ 17*4882a593Smuzhiyun #define PA_ROM 0xa0000000 /* EPROM */ 18*4882a593Smuzhiyun #define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */ 19*4882a593Smuzhiyun #define PA_FROM 0xa1000000 /* Flash-ROM */ 20*4882a593Smuzhiyun #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ 21*4882a593Smuzhiyun #define PA_EXT1 0xa4000000 22*4882a593Smuzhiyun #define PA_EXT1_SIZE 0x04000000 23*4882a593Smuzhiyun #define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */ 24*4882a593Smuzhiyun #define PA_SDRAM_SIZE 0x04000000 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define PA_EXT4 0xb0000000 27*4882a593Smuzhiyun #define PA_EXT4_SIZE 0x04000000 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define PA_PERIPHERAL 0xB0000000 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */ 32*4882a593Smuzhiyun #define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */ 33*4882a593Smuzhiyun #define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */ 34*4882a593Smuzhiyun #define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */ 35*4882a593Smuzhiyun #define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) /* MR-SHPC-01 I/O window base */ 36*4882a593Smuzhiyun #define MRSHPC_OPTION (PA_MRSHPC + 6) 37*4882a593Smuzhiyun #define MRSHPC_CSR (PA_MRSHPC + 8) 38*4882a593Smuzhiyun #define MRSHPC_ISR (PA_MRSHPC + 10) 39*4882a593Smuzhiyun #define MRSHPC_ICR (PA_MRSHPC + 12) 40*4882a593Smuzhiyun #define MRSHPC_CPWCR (PA_MRSHPC + 14) 41*4882a593Smuzhiyun #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) 42*4882a593Smuzhiyun #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) 43*4882a593Smuzhiyun #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) 44*4882a593Smuzhiyun #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) 45*4882a593Smuzhiyun #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) 46*4882a593Smuzhiyun #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) 47*4882a593Smuzhiyun #define MRSHPC_CDCR (PA_MRSHPC + 28) 48*4882a593Smuzhiyun #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */ 51*4882a593Smuzhiyun #define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */ 54*4882a593Smuzhiyun /* GPIO */ 55*4882a593Smuzhiyun #define FPGA_IN 0xb1840000UL 56*4882a593Smuzhiyun #define FPGA_OUT 0xb1840004UL 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define PORT_PECR 0xA4050108UL 59*4882a593Smuzhiyun #define PORT_PJCR 0xA4050110UL 60*4882a593Smuzhiyun #define PORT_PSELD 0xA4050154UL 61*4882a593Smuzhiyun #define PORT_PSELB 0xA4050150UL 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define PORT_PSELC 0xA4050152UL 64*4882a593Smuzhiyun #define PORT_PKCR 0xA4050112UL 65*4882a593Smuzhiyun #define PORT_PHCR 0xA405010EUL 66*4882a593Smuzhiyun #define PORT_PLCR 0xA4050114UL 67*4882a593Smuzhiyun #define PORT_PMCR 0xA4050116UL 68*4882a593Smuzhiyun #define PORT_PRCR 0xA405011CUL 69*4882a593Smuzhiyun #define PORT_PXCR 0xA4050148UL 70*4882a593Smuzhiyun #define PORT_PSELA 0xA405014EUL 71*4882a593Smuzhiyun #define PORT_PYCR 0xA405014AUL 72*4882a593Smuzhiyun #define PORT_PZCR 0xA405014CUL 73*4882a593Smuzhiyun #define PORT_HIZCRA 0xA4050158UL 74*4882a593Smuzhiyun #define PORT_HIZCRC 0xA405015CUL 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* IRQ */ 77*4882a593Smuzhiyun #define IRQ0_IRQ evt2irq(0x600) 78*4882a593Smuzhiyun #define IRQ1_IRQ evt2irq(0x620) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */ 81*4882a593Smuzhiyun #define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */ 82*4882a593Smuzhiyun #define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */ 83*4882a593Smuzhiyun #define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */ 84*4882a593Smuzhiyun #define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */ 85*4882a593Smuzhiyun #define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */ 86*4882a593Smuzhiyun #define SE7722_FPGA_IRQ_NR 6 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun struct irq_domain; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* arch/sh/boards/se/7722/irq.c */ 91*4882a593Smuzhiyun extern struct irq_domain *se7722_irq_domain; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun void init_se7722_IRQ(void); 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define __IO_PREFIX se7722 96*4882a593Smuzhiyun #include <asm/io_generic.h> 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #endif /* __ASM_SH_SE7722_H */ 99