1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2008 Renesas Solutions Corp. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Hitachi UL SolutionEngine 7721 Support. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_SH_SE7721_H 9*4882a593Smuzhiyun #define __ASM_SH_SE7721_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/sh_intc.h> 12*4882a593Smuzhiyun #include <asm/addrspace.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Box specific addresses. */ 15*4882a593Smuzhiyun #define SE_AREA0_WIDTH 2 /* Area0: 32bit */ 16*4882a593Smuzhiyun #define PA_ROM 0xa0000000 /* EPROM */ 17*4882a593Smuzhiyun #define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */ 18*4882a593Smuzhiyun #define PA_FROM 0xa1000000 /* Flash-ROM */ 19*4882a593Smuzhiyun #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ 20*4882a593Smuzhiyun #define PA_EXT1 0xa4000000 21*4882a593Smuzhiyun #define PA_EXT1_SIZE 0x04000000 22*4882a593Smuzhiyun #define PA_SDRAM 0xaC000000 /* SDRAM(Area3) 64MB */ 23*4882a593Smuzhiyun #define PA_SDRAM_SIZE 0x04000000 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define PA_EXT4 0xb0000000 26*4882a593Smuzhiyun #define PA_EXT4_SIZE 0x04000000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define PA_PERIPHERAL 0xB8000000 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define PA_PCIC PA_PERIPHERAL 31*4882a593Smuzhiyun #define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) 32*4882a593Smuzhiyun #define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) 33*4882a593Smuzhiyun #define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) 34*4882a593Smuzhiyun #define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) 35*4882a593Smuzhiyun #define MRSHPC_OPTION (PA_MRSHPC + 6) 36*4882a593Smuzhiyun #define MRSHPC_CSR (PA_MRSHPC + 8) 37*4882a593Smuzhiyun #define MRSHPC_ISR (PA_MRSHPC + 10) 38*4882a593Smuzhiyun #define MRSHPC_ICR (PA_MRSHPC + 12) 39*4882a593Smuzhiyun #define MRSHPC_CPWCR (PA_MRSHPC + 14) 40*4882a593Smuzhiyun #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) 41*4882a593Smuzhiyun #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) 42*4882a593Smuzhiyun #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) 43*4882a593Smuzhiyun #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) 44*4882a593Smuzhiyun #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) 45*4882a593Smuzhiyun #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) 46*4882a593Smuzhiyun #define MRSHPC_CDCR (PA_MRSHPC + 28) 47*4882a593Smuzhiyun #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define PA_LED 0xB6800000 /* 8bit LED */ 50*4882a593Smuzhiyun #define PA_FPGA 0xB7000000 /* FPGA base address */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define MRSHPC_IRQ0 evt2irq(0x340) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define FPGA_ILSR1 (PA_FPGA + 0x02) 55*4882a593Smuzhiyun #define FPGA_ILSR2 (PA_FPGA + 0x03) 56*4882a593Smuzhiyun #define FPGA_ILSR3 (PA_FPGA + 0x04) 57*4882a593Smuzhiyun #define FPGA_ILSR4 (PA_FPGA + 0x05) 58*4882a593Smuzhiyun #define FPGA_ILSR5 (PA_FPGA + 0x06) 59*4882a593Smuzhiyun #define FPGA_ILSR6 (PA_FPGA + 0x07) 60*4882a593Smuzhiyun #define FPGA_ILSR7 (PA_FPGA + 0x08) 61*4882a593Smuzhiyun #define FPGA_ILSR8 (PA_FPGA + 0x09) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun void init_se7721_IRQ(void); 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define __IO_PREFIX se7721 66*4882a593Smuzhiyun #include <asm/io_generic.h> 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif /* __ASM_SH_SE7721_H */ 69