1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_HITACHI_SE_H 3*4882a593Smuzhiyun #define __ASM_SH_HITACHI_SE_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * linux/include/asm-sh/hitachi_se.h 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2000 Kazumoto Kojima 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Hitachi SolutionEngine support 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #include <linux/sh_intc.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Box specific addresses. */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define PA_ROM 0x00000000 /* EPROM */ 17*4882a593Smuzhiyun #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ 18*4882a593Smuzhiyun #define PA_FROM 0x01000000 /* EPROM */ 19*4882a593Smuzhiyun #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ 20*4882a593Smuzhiyun #define PA_EXT1 0x04000000 21*4882a593Smuzhiyun #define PA_EXT1_SIZE 0x04000000 22*4882a593Smuzhiyun #define PA_EXT2 0x08000000 23*4882a593Smuzhiyun #define PA_EXT2_SIZE 0x04000000 24*4882a593Smuzhiyun #define PA_SDRAM 0x0c000000 25*4882a593Smuzhiyun #define PA_SDRAM_SIZE 0x04000000 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define PA_EXT4 0x12000000 28*4882a593Smuzhiyun #define PA_EXT4_SIZE 0x02000000 29*4882a593Smuzhiyun #define PA_EXT5 0x14000000 30*4882a593Smuzhiyun #define PA_EXT5_SIZE 0x04000000 31*4882a593Smuzhiyun #define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define PA_83902 0xb0000000 /* DP83902A */ 34*4882a593Smuzhiyun #define PA_83902_IF 0xb0040000 /* DP83902A remote io port */ 35*4882a593Smuzhiyun #define PA_83902_RST 0xb0080000 /* DP83902A reset port */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */ 38*4882a593Smuzhiyun #define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */ 39*4882a593Smuzhiyun #define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */ 40*4882a593Smuzhiyun #define PA_LED 0xb0c00000 /* LED */ 41*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7705) 42*4882a593Smuzhiyun #define PA_BCR 0xb0e00000 43*4882a593Smuzhiyun #else 44*4882a593Smuzhiyun #define PA_BCR 0xb1400000 /* FPGA */ 45*4882a593Smuzhiyun #endif 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ 48*4882a593Smuzhiyun #define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ 49*4882a593Smuzhiyun #define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ 50*4882a593Smuzhiyun #define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ 51*4882a593Smuzhiyun #define MRSHPC_OPTION (PA_MRSHPC + 6) 52*4882a593Smuzhiyun #define MRSHPC_CSR (PA_MRSHPC + 8) 53*4882a593Smuzhiyun #define MRSHPC_ISR (PA_MRSHPC + 10) 54*4882a593Smuzhiyun #define MRSHPC_ICR (PA_MRSHPC + 12) 55*4882a593Smuzhiyun #define MRSHPC_CPWCR (PA_MRSHPC + 14) 56*4882a593Smuzhiyun #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) 57*4882a593Smuzhiyun #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) 58*4882a593Smuzhiyun #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) 59*4882a593Smuzhiyun #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) 60*4882a593Smuzhiyun #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) 61*4882a593Smuzhiyun #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) 62*4882a593Smuzhiyun #define MRSHPC_CDCR (PA_MRSHPC + 28) 63*4882a593Smuzhiyun #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define BCR_ILCRA (PA_BCR + 0) 66*4882a593Smuzhiyun #define BCR_ILCRB (PA_BCR + 2) 67*4882a593Smuzhiyun #define BCR_ILCRC (PA_BCR + 4) 68*4882a593Smuzhiyun #define BCR_ILCRD (PA_BCR + 6) 69*4882a593Smuzhiyun #define BCR_ILCRE (PA_BCR + 8) 70*4882a593Smuzhiyun #define BCR_ILCRF (PA_BCR + 10) 71*4882a593Smuzhiyun #define BCR_ILCRG (PA_BCR + 12) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7709) 74*4882a593Smuzhiyun #define INTC_IRR0 0xa4000004UL 75*4882a593Smuzhiyun #define INTC_IRR1 0xa4000006UL 76*4882a593Smuzhiyun #define INTC_IRR2 0xa4000008UL 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define INTC_ICR0 0xfffffee0UL 79*4882a593Smuzhiyun #define INTC_ICR1 0xa4000010UL 80*4882a593Smuzhiyun #define INTC_ICR2 0xa4000012UL 81*4882a593Smuzhiyun #define INTC_INTER 0xa4000014UL 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define INTC_IPRC 0xa4000016UL 84*4882a593Smuzhiyun #define INTC_IPRD 0xa4000018UL 85*4882a593Smuzhiyun #define INTC_IPRE 0xa400001aUL 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define IRQ0_IRQ evt2irq(0x600) 88*4882a593Smuzhiyun #define IRQ1_IRQ evt2irq(0x620) 89*4882a593Smuzhiyun #endif 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7705) 92*4882a593Smuzhiyun #define IRQ_STNIC evt2irq(0x380) 93*4882a593Smuzhiyun #define IRQ_CFCARD evt2irq(0x3c0) 94*4882a593Smuzhiyun #else 95*4882a593Smuzhiyun #define IRQ_STNIC evt2irq(0x340) 96*4882a593Smuzhiyun #define IRQ_CFCARD evt2irq(0x2e0) 97*4882a593Smuzhiyun #endif 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* SH Ether support (SH7710/SH7712) */ 100*4882a593Smuzhiyun /* Base address */ 101*4882a593Smuzhiyun #define SH_ETH0_BASE 0xA7000000 102*4882a593Smuzhiyun #define SH_ETH1_BASE 0xA7000400 103*4882a593Smuzhiyun #define SH_TSU_BASE 0xA7000800 104*4882a593Smuzhiyun /* PHY ID */ 105*4882a593Smuzhiyun #if defined(CONFIG_CPU_SUBTYPE_SH7710) 106*4882a593Smuzhiyun # define PHY_ID 0x00 107*4882a593Smuzhiyun #elif defined(CONFIG_CPU_SUBTYPE_SH7712) 108*4882a593Smuzhiyun # define PHY_ID 0x01 109*4882a593Smuzhiyun #endif 110*4882a593Smuzhiyun /* Ether IRQ */ 111*4882a593Smuzhiyun #define SH_ETH0_IRQ evt2irq(0xc00) 112*4882a593Smuzhiyun #define SH_ETH1_IRQ evt2irq(0xc20) 113*4882a593Smuzhiyun #define SH_TSU_IRQ evt2irq(0xc40) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun void init_se_IRQ(void); 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define __IO_PREFIX se 118*4882a593Smuzhiyun #include <asm/io_generic.h> 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #endif /* __ASM_SH_HITACHI_SE_H */ 121