1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * include/asm-sh/dreamcast/sysasic.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Definitions for the Dreamcast System ASIC and related peripherals. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (c) 2001 M. R. Brown <mrbrown@linuxdc.org> 8*4882a593Smuzhiyun * Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org> 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * This file is part of the LinuxDC project (www.linuxdc.org) 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #ifndef __ASM_SH_DREAMCAST_SYSASIC_H 13*4882a593Smuzhiyun #define __ASM_SH_DREAMCAST_SYSASIC_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <asm/irq.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Hardware events - 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun Each of these events correspond to a bit within the Event Mask Registers/ 20*4882a593Smuzhiyun Event Status Registers. Because of the virtual IRQ numbering scheme, a 21*4882a593Smuzhiyun base offset must be used when calculating the virtual IRQ that each event 22*4882a593Smuzhiyun takes. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define HW_EVENT_IRQ_BASE 48 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* IRQ 13 */ 28*4882a593Smuzhiyun #define HW_EVENT_VSYNC (HW_EVENT_IRQ_BASE + 5) /* VSync */ 29*4882a593Smuzhiyun #define HW_EVENT_MAPLE_DMA (HW_EVENT_IRQ_BASE + 12) /* Maple DMA complete */ 30*4882a593Smuzhiyun #define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */ 31*4882a593Smuzhiyun #define HW_EVENT_G2_DMA (HW_EVENT_IRQ_BASE + 15) /* G2 DMA complete */ 32*4882a593Smuzhiyun #define HW_EVENT_PVR2_DMA (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* IRQ 11 */ 35*4882a593Smuzhiyun #define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */ 36*4882a593Smuzhiyun #define HW_EVENT_AICA_SYS (HW_EVENT_IRQ_BASE + 33) /* AICA-related */ 37*4882a593Smuzhiyun #define HW_EVENT_EXTERNAL (HW_EVENT_IRQ_BASE + 35) /* Ext. (expansion) */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define HW_EVENT_IRQ_MAX (HW_EVENT_IRQ_BASE + 95) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* arch/sh/boards/mach-dreamcast/irq.c */ 42*4882a593Smuzhiyun extern int systemasic_irq_demux(int); 43*4882a593Smuzhiyun extern void systemasic_irq_init(void); 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #endif /* __ASM_SH_DREAMCAST_SYSASIC_H */ 46*4882a593Smuzhiyun 47