1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * include/asm-sh/dreamcast/dma.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2003 Paul Mundt 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __ASM_SH_DREAMCAST_DMA_H 8*4882a593Smuzhiyun #define __ASM_SH_DREAMCAST_DMA_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Number of DMA channels */ 11*4882a593Smuzhiyun #define G2_NR_DMA_CHANNELS 4 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Channels for cascading */ 14*4882a593Smuzhiyun #define PVR2_CASCADE_CHAN 2 15*4882a593Smuzhiyun #define G2_CASCADE_CHAN 3 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* PVR2 DMA Registers */ 18*4882a593Smuzhiyun #define PVR2_DMA_BASE 0xa05f6800 19*4882a593Smuzhiyun #define PVR2_DMA_ADDR (PVR2_DMA_BASE + 0) 20*4882a593Smuzhiyun #define PVR2_DMA_COUNT (PVR2_DMA_BASE + 4) 21*4882a593Smuzhiyun #define PVR2_DMA_MODE (PVR2_DMA_BASE + 8) 22*4882a593Smuzhiyun #define PVR2_DMA_LMMODE0 (PVR2_DMA_BASE + 132) 23*4882a593Smuzhiyun #define PVR2_DMA_LMMODE1 (PVR2_DMA_BASE + 136) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* G2 DMA Register */ 26*4882a593Smuzhiyun #define G2_DMA_BASE 0xa05f7800 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #endif /* __ASM_SH_DREAMCAST_DMA_H */ 29*4882a593Smuzhiyun 30