1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_RENESAS_SH7785LCR_H 3*4882a593Smuzhiyun #define __ASM_SH_RENESAS_SH7785LCR_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * This board has 2 physical memory maps. 7*4882a593Smuzhiyun * It can be changed with DIP switch(S2-5). 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * phys address | S2-5 = OFF | S2-5 = ON 10*4882a593Smuzhiyun * -----------------------------+---------------+--------------- 11*4882a593Smuzhiyun * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash 12*4882a593Smuzhiyun * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD 13*4882a593Smuzhiyun * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C 14*4882a593Smuzhiyun * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM 15*4882a593Smuzhiyun * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM 16*4882a593Smuzhiyun * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107 17*4882a593Smuzhiyun * 0x14000000 - 0x17ffffff(CS5) | reserved | USB 18*4882a593Smuzhiyun * 0x18000000 - 0x1bffffff(CS6) | reserved | SD 19*4882a593Smuzhiyun * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use) 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define NOR_FLASH_ADDR 0x00000000 24*4882a593Smuzhiyun #define NOR_FLASH_SIZE 0x04000000 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define PLD_BASE_ADDR 0x04000000 27*4882a593Smuzhiyun #define PLD_PCICR (PLD_BASE_ADDR + 0x00) 28*4882a593Smuzhiyun #define PLD_LCD_BK_CONTR (PLD_BASE_ADDR + 0x02) 29*4882a593Smuzhiyun #define PLD_LOCALCR (PLD_BASE_ADDR + 0x04) 30*4882a593Smuzhiyun #define PLD_POFCR (PLD_BASE_ADDR + 0x06) 31*4882a593Smuzhiyun #define PLD_LEDCR (PLD_BASE_ADDR + 0x08) 32*4882a593Smuzhiyun #define PLD_SWSR (PLD_BASE_ADDR + 0x0a) 33*4882a593Smuzhiyun #define PLD_VERSR (PLD_BASE_ADDR + 0x0c) 34*4882a593Smuzhiyun #define PLD_MMSR (PLD_BASE_ADDR + 0x0e) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define PCA9564_ADDR 0x06000000 /* I2C */ 37*4882a593Smuzhiyun #define PCA9564_SIZE 0x00000100 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define PCA9564_PROTO_32BIT_ADDR 0x14000000 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define SM107_MEM_ADDR 0x10000000 42*4882a593Smuzhiyun #define SM107_MEM_SIZE 0x00e00000 43*4882a593Smuzhiyun #define SM107_REG_ADDR 0x13e00000 44*4882a593Smuzhiyun #define SM107_REG_SIZE 0x00200000 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS) 47*4882a593Smuzhiyun #define R8A66597_ADDR 0x14000000 /* USB */ 48*4882a593Smuzhiyun #define CG200_ADDR 0x18000000 /* SD */ 49*4882a593Smuzhiyun #else 50*4882a593Smuzhiyun #define R8A66597_ADDR 0x08000000 51*4882a593Smuzhiyun #define CG200_ADDR 0x0c000000 52*4882a593Smuzhiyun #endif 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define R8A66597_SIZE 0x00000100 55*4882a593Smuzhiyun #define CG200_SIZE 0x00010000 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #endif /* __ASM_SH_RENESAS_SH7785LCR_H */ 58*4882a593Smuzhiyun 59