1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __MACH_SH2007_H 3*4882a593Smuzhiyun #define __MACH_SH2007_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define CS5BCR 0xff802050 6*4882a593Smuzhiyun #define CS5WCR 0xff802058 7*4882a593Smuzhiyun #define CS5PCR 0xff802070 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define BUS_SZ8 1 10*4882a593Smuzhiyun #define BUS_SZ16 2 11*4882a593Smuzhiyun #define BUS_SZ32 3 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define PCMCIA_IODYN 1 14*4882a593Smuzhiyun #define PCMCIA_ATA 0 15*4882a593Smuzhiyun #define PCMCIA_IO8 2 16*4882a593Smuzhiyun #define PCMCIA_IO16 3 17*4882a593Smuzhiyun #define PCMCIA_COMM8 4 18*4882a593Smuzhiyun #define PCMCIA_COMM16 5 19*4882a593Smuzhiyun #define PCMCIA_ATTR8 6 20*4882a593Smuzhiyun #define PCMCIA_ATTR16 7 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define TYPE_SRAM 0 23*4882a593Smuzhiyun #define TYPE_PCMCIA 4 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */ 26*4882a593Smuzhiyun #define IWW5 0 27*4882a593Smuzhiyun #define IWW6 3 28*4882a593Smuzhiyun /* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */ 29*4882a593Smuzhiyun #define IWRWD5 2 30*4882a593Smuzhiyun #define IWRWD6 2 31*4882a593Smuzhiyun /* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */ 32*4882a593Smuzhiyun #define IWRWS5 2 33*4882a593Smuzhiyun #define IWRWS6 2 34*4882a593Smuzhiyun /* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */ 35*4882a593Smuzhiyun #define IWRRD5 2 36*4882a593Smuzhiyun #define IWRRD6 2 37*4882a593Smuzhiyun /* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */ 38*4882a593Smuzhiyun #define IWRRS5 0 39*4882a593Smuzhiyun #define IWRRS6 2 40*4882a593Smuzhiyun /* burst count (0-3:4,8,16,32) */ 41*4882a593Smuzhiyun #define BST5 0 42*4882a593Smuzhiyun #define BST6 0 43*4882a593Smuzhiyun /* bus size */ 44*4882a593Smuzhiyun #define SZ5 BUS_SZ16 45*4882a593Smuzhiyun #define SZ6 BUS_SZ16 46*4882a593Smuzhiyun /* RD hold for SRAM (0-1:0,1) */ 47*4882a593Smuzhiyun #define RDSPL5 0 48*4882a593Smuzhiyun #define RDSPL6 0 49*4882a593Smuzhiyun /* Burst pitch (0-7:0,1,2,3,4,5,6,7) */ 50*4882a593Smuzhiyun #define BW5 0 51*4882a593Smuzhiyun #define BW6 0 52*4882a593Smuzhiyun /* Multiplex (0-1:0,1) */ 53*4882a593Smuzhiyun #define MPX5 0 54*4882a593Smuzhiyun #define MPX6 0 55*4882a593Smuzhiyun /* device type */ 56*4882a593Smuzhiyun #define TYPE5 TYPE_PCMCIA 57*4882a593Smuzhiyun #define TYPE6 TYPE_PCMCIA 58*4882a593Smuzhiyun /* address setup before assert CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */ 59*4882a593Smuzhiyun #define ADS5 0 60*4882a593Smuzhiyun #define ADS6 0 61*4882a593Smuzhiyun /* address hold after negate CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */ 62*4882a593Smuzhiyun #define ADH5 0 63*4882a593Smuzhiyun #define ADH6 0 64*4882a593Smuzhiyun /* CSn assert to RD assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ 65*4882a593Smuzhiyun #define RDS5 0 66*4882a593Smuzhiyun #define RDS6 0 67*4882a593Smuzhiyun /* RD negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ 68*4882a593Smuzhiyun #define RDH5 0 69*4882a593Smuzhiyun #define RDH6 0 70*4882a593Smuzhiyun /* CSn assert to WE assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ 71*4882a593Smuzhiyun #define WTS5 0 72*4882a593Smuzhiyun #define WTS6 0 73*4882a593Smuzhiyun /* WE negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ 74*4882a593Smuzhiyun #define WTH5 0 75*4882a593Smuzhiyun #define WTH6 0 76*4882a593Smuzhiyun /* BS hold (0-1:1,2) */ 77*4882a593Smuzhiyun #define BSH5 0 78*4882a593Smuzhiyun #define BSH6 0 79*4882a593Smuzhiyun /* wait cycle (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */ 80*4882a593Smuzhiyun #define IW5 6 /* 60ns PIO mode 4 */ 81*4882a593Smuzhiyun #define IW6 15 /* 250ns */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define SAA5 PCMCIA_IODYN /* IDE area b4000000-b5ffffff */ 84*4882a593Smuzhiyun #define SAB5 PCMCIA_IODYN /* CF area b6000000-b7ffffff */ 85*4882a593Smuzhiyun #define PCWA5 0 /* additional wait A (0-3:0,15,30,50) */ 86*4882a593Smuzhiyun #define PCWB5 0 /* additional wait B (0-3:0,15,30,50) */ 87*4882a593Smuzhiyun /* wait B (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */ 88*4882a593Smuzhiyun #define PCIW5 12 89*4882a593Smuzhiyun /* Address->OE/WE assert delay A (0-7:0,1,2,3,6,9,12,15) */ 90*4882a593Smuzhiyun #define TEDA5 2 91*4882a593Smuzhiyun /* Address->OE/WE assert delay B (0-7:0,1,2,3,6,9,12,15) */ 92*4882a593Smuzhiyun #define TEDB5 4 93*4882a593Smuzhiyun /* OE/WE negate->Address delay A (0-7:0,1,2,3,6,9,12,15) */ 94*4882a593Smuzhiyun #define TEHA5 2 95*4882a593Smuzhiyun /* OE/WE negate->Address delay B (0-7:0,1,2,3,6,9,12,15) */ 96*4882a593Smuzhiyun #define TEHB5 3 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define CS5BCR_D ((IWW5<<28)|(IWRWD5<<24)|(IWRWS5<<20)| \ 99*4882a593Smuzhiyun (IWRRD5<<16)|(IWRRS5<<12)|(BST5<<10)| \ 100*4882a593Smuzhiyun (SZ5<<8)|(RDSPL5<<7)|(BW5<<4)|(MPX5<<3)|TYPE5) 101*4882a593Smuzhiyun #define CS5WCR_D ((ADS5<<28)|(ADH5<<24)|(RDS5<<20)| \ 102*4882a593Smuzhiyun (RDH5<<16)|(WTS5<<12)|(WTH5<<8)|(BSH5<<4)|IW5) 103*4882a593Smuzhiyun #define CS5PCR_D ((SAA5<<28)|(SAB5<<24)|(PCWA5<<22)| \ 104*4882a593Smuzhiyun (PCWB5<<20)|(PCIW5<<16)|(TEDA5<<12)| \ 105*4882a593Smuzhiyun (TEDB5<<8)|(TEHA5<<4)|TEHB5) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define SMC0_BASE 0xb0800000 /* eth0 */ 108*4882a593Smuzhiyun #define SMC1_BASE 0xb0900000 /* eth1 */ 109*4882a593Smuzhiyun #define CF_BASE 0xb6100000 /* Compact Flash (I/O area) */ 110*4882a593Smuzhiyun #define IDE_BASE 0xb4000000 /* IDE */ 111*4882a593Smuzhiyun #define PC104_IO_BASE 0xb8000000 112*4882a593Smuzhiyun #define PC104_MEM_BASE 0xba000000 113*4882a593Smuzhiyun #define SMC_IO_SIZE 0x100 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define CF_OFFSET 0x1f0 116*4882a593Smuzhiyun #define IDE_OFFSET 0x170 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #endif /* __MACH_SH2007_H */ 119