1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_RENESAS_SDK7780_H 3*4882a593Smuzhiyun #define __ASM_SH_RENESAS_SDK7780_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * linux/include/asm-sh/sdk7780.h 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Renesas Solutions SH7780 SDK Support 9*4882a593Smuzhiyun * Copyright (C) 2008 Nicholas Beck <nbeck@mpc-data.co.uk> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #include <linux/sh_intc.h> 12*4882a593Smuzhiyun #include <asm/addrspace.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Box specific addresses. */ 15*4882a593Smuzhiyun #define SE_AREA0_WIDTH 4 /* Area0: 32bit */ 16*4882a593Smuzhiyun #define PA_ROM 0xa0000000 /* EPROM */ 17*4882a593Smuzhiyun #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ 18*4882a593Smuzhiyun #define PA_FROM 0xa0800000 /* Flash-ROM */ 19*4882a593Smuzhiyun #define PA_FROM_SIZE 0x00400000 /* Flash-ROM size 4M byte */ 20*4882a593Smuzhiyun #define PA_EXT1 0xa4000000 21*4882a593Smuzhiyun #define PA_EXT1_SIZE 0x04000000 22*4882a593Smuzhiyun #define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */ 23*4882a593Smuzhiyun #define PA_SDRAM_SIZE 0x08000000 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define PA_EXT4 0xb0000000 26*4882a593Smuzhiyun #define PA_EXT4_SIZE 0x04000000 27*4882a593Smuzhiyun #define PA_EXT_USER PA_EXT4 /* User Expansion Space */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define PA_PERIPHERAL PA_AREA5_IO 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* SRAM/Reserved */ 32*4882a593Smuzhiyun #define PA_RESERVED (PA_PERIPHERAL + 0) 33*4882a593Smuzhiyun /* FPGA base address */ 34*4882a593Smuzhiyun #define PA_FPGA (PA_PERIPHERAL + 0x01000000) 35*4882a593Smuzhiyun /* SMC LAN91C111 */ 36*4882a593Smuzhiyun #define PA_LAN (PA_PERIPHERAL + 0x01800000) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define FPGA_SRSTR (PA_FPGA + 0x000) /* System reset */ 40*4882a593Smuzhiyun #define FPGA_IRQ0SR (PA_FPGA + 0x010) /* IRQ0 status */ 41*4882a593Smuzhiyun #define FPGA_IRQ0MR (PA_FPGA + 0x020) /* IRQ0 mask */ 42*4882a593Smuzhiyun #define FPGA_BDMR (PA_FPGA + 0x030) /* Board operating mode */ 43*4882a593Smuzhiyun #define FPGA_INTT0PRTR (PA_FPGA + 0x040) /* Interrupt test mode0 port */ 44*4882a593Smuzhiyun #define FPGA_INTT0SELR (PA_FPGA + 0x050) /* Int. test mode0 select */ 45*4882a593Smuzhiyun #define FPGA_INTT1POLR (PA_FPGA + 0x060) /* Int. test mode0 polarity */ 46*4882a593Smuzhiyun #define FPGA_NMIR (PA_FPGA + 0x070) /* NMI source */ 47*4882a593Smuzhiyun #define FPGA_NMIMR (PA_FPGA + 0x080) /* NMI mask */ 48*4882a593Smuzhiyun #define FPGA_IRQR (PA_FPGA + 0x090) /* IRQX source */ 49*4882a593Smuzhiyun #define FPGA_IRQMR (PA_FPGA + 0x0A0) /* IRQX mask */ 50*4882a593Smuzhiyun #define FPGA_SLEDR (PA_FPGA + 0x0B0) /* LED control */ 51*4882a593Smuzhiyun #define PA_LED FPGA_SLEDR 52*4882a593Smuzhiyun #define FPGA_MAPSWR (PA_FPGA + 0x0C0) /* Map switch */ 53*4882a593Smuzhiyun #define FPGA_FPVERR (PA_FPGA + 0x0D0) /* FPGA version */ 54*4882a593Smuzhiyun #define FPGA_FPDATER (PA_FPGA + 0x0E0) /* FPGA date */ 55*4882a593Smuzhiyun #define FPGA_RSE (PA_FPGA + 0x100) /* Reset source */ 56*4882a593Smuzhiyun #define FPGA_EASR (PA_FPGA + 0x110) /* External area select */ 57*4882a593Smuzhiyun #define FPGA_SPER (PA_FPGA + 0x120) /* Serial port enable */ 58*4882a593Smuzhiyun #define FPGA_IMSR (PA_FPGA + 0x130) /* Interrupt mode select */ 59*4882a593Smuzhiyun #define FPGA_PCIMR (PA_FPGA + 0x140) /* PCI Mode */ 60*4882a593Smuzhiyun #define FPGA_DIPSWMR (PA_FPGA + 0x150) /* DIPSW monitor */ 61*4882a593Smuzhiyun #define FPGA_FPODR (PA_FPGA + 0x160) /* Output port data */ 62*4882a593Smuzhiyun #define FPGA_ATAESR (PA_FPGA + 0x170) /* ATA extended bus status */ 63*4882a593Smuzhiyun #define FPGA_IRQPOLR (PA_FPGA + 0x180) /* IRQx polarity */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define SDK7780_NR_IRL 15 67*4882a593Smuzhiyun /* IDE/ATA interrupt */ 68*4882a593Smuzhiyun #define IRQ_CFCARD evt2irq(0x3c0) 69*4882a593Smuzhiyun /* SMC interrupt */ 70*4882a593Smuzhiyun #define IRQ_ETHERNET evt2irq(0x2c0) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* arch/sh/boards/renesas/sdk7780/irq.c */ 74*4882a593Smuzhiyun void init_sdk7780_IRQ(void); 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define __IO_PREFIX sdk7780 77*4882a593Smuzhiyun #include <asm/io_generic.h> 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #endif /* __ASM_SH_RENESAS_SDK7780_H */ 80